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1. 发明授权

US5578175A Process for manufacturing iridium and palladium oxides-coated titanium electrode and the electrode produced thereby 失效
标题翻译：用于制造铱和钯氧化物涂覆的钛电极的方法以及由此制备的电极
公开(公告)号：US5578175A
公开(公告)日：1996-11-26
申请号：US291452
申请日：1994-08-16
申请人： Kwang-Lung Lin , Ju-Tung Lee , Yuan-Po Lee
发明人： Kwang-Lung Lin , Ju-Tung Lee , Yuan-Po Lee
IPC分类号： C25B11/04 , C25B11/10 , C25D17/12 , H01M4/04 , C25D5/00 , C25D5/18
CPC分类号： C25B11/0478
摘要： A process for manufacturing an iridium and palladium oxides-coated titanium electrode comprises preparing a titanium substrate having a surface, applying iridium and palladium to be formed on the surface of the titanium substrate, and heat-treating the iridium and palladium oxides-applied titanium substrate to obtain an iridium and palladium oxides-coated titanium electrode. This invention provides a process for obtaining a coated titanium electrode having therein a good adhesion between the coating material and the titanium electrode, and having an excellent electrochemical stability and a superior catalytic activity in an acidic environment.
摘要翻译：制造铱和钯氧化物涂覆的钛电极的方法包括制备具有表面的钛基板，在钛基板的表面上施加要形成的铱和钯，并且对所述铱和钯氧化物涂覆的钛基板进行热处理以获得铱和氧化钯涂覆的钛电极。本发明提供一种获得涂层钛电极的方法，其中涂层材料和钛电极之间具有良好的粘附性，并且在酸性环境中具有优异的电化学稳定性和优异的催化活性。

2. 发明授权

US06837947B2 Lead-free solder 失效
标题翻译：无铅焊料
公开(公告)号：US06837947B2
公开(公告)日：2005-01-04
申请号：US10045004
申请日：2002-01-15
申请人： Kwang-Lung Lin , Kang-I Chen , Shou-Chang Cheng , Jia-Wei Huang
发明人： Kwang-Lung Lin , Kang-I Chen , Shou-Chang Cheng , Jia-Wei Huang
IPC分类号： B23K35/26 , C22C13/00 , B23K35/00
CPC分类号： B23K35/262 , C22C13/00
摘要： This invention discloses a lead-free Sn—Zn—Al—Ag solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, and the balance of Sn; and a lead-free Sn—Zn—Al—Ag—Ga solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, up to 4.0 wt % of Ga; and the balance of Sn. The lead-free solder alloys of the present invention have better tensile strength and elongation than the conventional Sn—Pb solder alloys. In addition, the lead-free solder alloys of the present invention have a melting point lower than 200° C., which is close to the 183.5° C. of an eutectic Sn—Pb alloy.

3. 发明申请

US20030133826A1 Lead-free solder 失效
标题翻译：无铅焊料
公开(公告)号：US20030133826A1
公开(公告)日：2003-07-17
申请号：US10045004
申请日：2002-01-15
申请人： Kwang-Lung LIN
发明人： Kwang-Lung Lin , Kang-I Chen , Shou-Chang Cheng , Jia-Wei Huang
IPC分类号： C22C013/00
CPC分类号： B23K35/262 , C22C13/00
摘要： This invention discloses a lead-free SnnullZnnullAlnullAg solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, and the balance of Sn; and a lead-free SnnullZnnullAlnullAgnullGa solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, up to 4.0 wt % of Ga; and the balance of Sn. The lead-free solder alloys of the present invention have better tensile strength and elongation than the conventional SnnullPb solder alloys. In addition, the lead-free solder alloys of the present invention have a melting point lower than 200null C., which is close to the 183.5null C. of an eutectic SnnullPb alloy.
摘要翻译：本发明公开了一种无铅Sn-Zn-Al-Ag焊料合金，其由7-10重量％的Zn，至多0.5重量％的Al，至多4.0重量％的Ag组成，余量为Sn ; 和无铅Sn-Zn-Al-Ag-Ga焊料合金，其由7-10重量％的Zn，至多0.5重量％的Al，至多4.0重量％的Ag，至多4.0重量％的Ga 和Sn的平衡。本发明的无铅焊料合金具有比常规Sn-Pb焊料合金更好的拉伸强度和伸长率。此外，本发明的无铅焊料合金的熔点低于200℃，接近于共晶Sn-Pb合金的183.5℃。

4. 发明授权

US6153503A Continuous process for producing solder bumps on electrodes of semiconductor chips 失效
标题翻译：用于在半导体芯片的电极上制造焊料凸块的连续工艺
公开(公告)号：US6153503A
公开(公告)日：2000-11-28
申请号：US37635
申请日：1998-03-10
申请人： Kwang-Lung Lin , Chih-Mei Yu , Wen-Hsiuan Chao
发明人： Kwang-Lung Lin , Chih-Mei Yu , Wen-Hsiuan Chao
IPC分类号： H01L21/60 , H01L23/485 , H01L21/44
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/15787
摘要： A process for producing solder bumps on metal electrodes, such as Al electrodes, of a semiconductor wafer, such as silicon wafer, involves the formation of the under bump metallurgies (UBM) on the electrodes. The solder bumps are then formed on the under bump metallurgies by wave soldering. The under bump metallurgies consist of a diffusion barrier layer formed on the metal electrodes, and a wetting layer formed on the diffusion barrier layer.
摘要翻译：在诸如硅晶片的半导体晶片的诸如Al电极的金属电极上制造焊料凸块的工艺涉及在电极上形成凸块下的金属（UBM）。然后通过波峰焊在凸块下金属上形成焊料凸块。凸块下冶金由形成在金属电极上的扩散阻挡层和形成在扩散阻挡层上的润湿层组成。

5. 发明授权

US5795619A Solder bump fabricated method incorporate with electroless deposit and dip solder 失效
标题翻译：焊接凸块制造方法结合无电沉积和浸焊
公开(公告)号：US5795619A
公开(公告)日：1998-08-18
申请号：US571401
申请日：1995-12-13
申请人： Kwang-Lung Lin , Chwan-Ying Lee
发明人： Kwang-Lung Lin , Chwan-Ying Lee
IPC分类号： C23C18/31 , C23C18/50 , B05D5/12
CPC分类号： C23C18/50 , C23C18/31
摘要： A process for preparing a solder bump can be prepared by the following procedure. The chip package was cleaned with an alkali or acid solution followed by Zn displacement (zincating)in a displacement solution which comprises NaOH, Z.sub.n o, potassium sodium tartrate and sodium nitrate. After zinc displacement the chip package was performed the electroless Ni--Cu--P deposit in the strong reducing solution which contains NaH.sub.2 PO.sub.2. The chip package deposited with Ni--Cu--P was then dipped into an organic solution as flux which is a mixture of the stearic acid and glutamic acid. Finally, dip soldering of the Ni--Cu--P deposited chip packages in a molten solder bath at a temperature 40.degree..about.80.degree. C. higher than the melting point of the corresponding Pb--Sn alloy.
摘要翻译：制备焊料凸点的方法可以通过以下步骤制备。用碱或酸溶液清洗芯片包装，然后在包含NaOH，Zno，酒石酸钾钠和硝酸钠的置换溶液中进行Zn置换（锌化）。锌置换后，在含有NaH2PO2的强还原溶液中进行无电解Ni-Cu-P沉积物的芯片封装。然后将沉积有Ni-Cu-P的芯片封装浸入作为硬脂酸和谷氨酸的混合物的助熔剂的有机溶液中。最后，将Ni-Cu-P沉积的芯片封装浸入熔融焊料浴中，比相应的Pb-Sn合金的熔点高40℃。

6. 发明授权

US5583073A Method for producing electroless barrier layer and solder bump on chip 失效
标题翻译：在芯片上制造无电解屏障层和焊料凸块的方法
公开(公告)号：US5583073A
公开(公告)日：1996-12-10
申请号：US368847
申请日：1995-01-05
申请人： Kwang-Lung Lin , Chwan-Ying Lee
发明人： Kwang-Lung Lin , Chwan-Ying Lee
IPC分类号： C23C18/31 , C23C18/36 , C23C18/44 , H01L21/60 , H01L21/28
CPC分类号： C23C18/31 , C23C18/36 , C23C18/44 , H01L24/11 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253
摘要： The present method for producing a barrier layer and a solder bump on a chip includes: a) providing a silicon chip with a bump base; b) forming a metal pad, e.g. an aluminum pad, on the bump base; c) having the metal pad contact with a solution containing about 120.about.150 g/l NaOH, 20.about.25 g/l ZnO, 1 g/l NaNO.sub.3 and 45.about.55 g/l C.sub.4 H.sub.4 KNaO.sub.6 .multidot.4H.sub.2 O to form thereon a zinc layer, and preferably further containing tartaric acid for reducing a dissolving rate of the metal pad.; d) having the zinc layer contact with a deposition solution to deposit thereon an electroless barrier layer, e.g. an electroless Ni-P layer; and e) dipping the resulting silicon chip into a molten solder bath to form a solder bump on the electroless barrier layer. The present invention is a simple process for manufacturing an electroless Ni-P and a solder bump on a chip.
摘要翻译：本发明的制造芯片上的阻挡层和焊料凸点的方法包括：a）提供具有凸点基底的硅芯片; b）形成金属垫，例如一个铝垫，在凸点上; c）使金属焊盘与含有约120％150g / l NaOH，20％25g / l ZnO，1g / l NaNO 3和45％45g / l C 4 H 4 KNaO 6 x 4 H 2 O的溶液接触，在其上形成锌层，优选还含有酒石酸以降低金属垫的溶解速率; d）使锌层与沉积溶液接触以在其上沉积无电阻挡层，例如，无电Ni-P层; 以及e）将所得到的硅芯片浸入熔融焊料浴中，以在无电阻挡层上形成焊料凸块。本发明是在芯片上制造无电解Ni-P和焊料凸块的简单方法。

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