专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08710941B2 High-order harmonic device of cavity filter 失效
标题翻译：谐波滤波器的高次谐波器件
公开(公告)号：US08710941B2
公开(公告)日：2014-04-29
申请号：US13020444
申请日：2011-02-03
申请人： Chien-Chih Lee , Wei-Chin Hsu , Hsien-Wen Liu
发明人： Chien-Chih Lee , Wei-Chin Hsu , Hsien-Wen Liu
IPC分类号： H01P1/205 , H01P7/04
CPC分类号： H01P1/205 , H01P1/2053 , H01P7/04
摘要： A high-order harmonic device of a cavity filter including a base and a lid cover the base is disclosed. The base has a through groove connecting to an upper and a lower portion. The base has a plurality of output terminal with metallic conductor extending into the inner side formed on the surface of the sidewall. The base has resonance space formed indented to receive the metallic conductor and extending to connect to the through groove. The lid has a plurality of threading holes formed corresponding to chambers and partitions received with adjusting elements for height adjustment. The adjusting elements has the resonance bars corresponding to every chamber and the suppressing bars corresponding to every partition. By adjusting suppressing bar and the partition to a predetermined distance, the space of the channel for transmitting the high-order harmonic wave can be reduced to suppress noise produced by high-order harmonic wave.
摘要翻译：公开了一种包括基座和盖子覆盖基座的空腔滤波器的高次谐波装置。基部具有连接到上部和下部的通孔。基座具有多个输出端子，金属导体延伸到形成在侧壁表面上的内侧。底座具有形成为凹入的谐振空间，用于容纳金属导体并延伸以连接到通孔。所述盖具有多个对应于室和隔板形成的穿孔，所述隔间和隔板被接纳有用于高度调节的调节元件。调节元件具有对应于每个室的共振杆和对应于每个分区的抑制棒。通过将抑制棒和隔板调节到预定距离，可以减少用于发送高次谐波的通道的空间，以抑制由高次谐波产生的噪声。

2. 发明申请

US20120200374A1 HIGH-ORDER HARMONIC DEVICE OF CAVITY FILTER 失效
标题翻译：高性能滤波器谐波器件
公开(公告)号：US20120200374A1
公开(公告)日：2012-08-09
申请号：US13020444
申请日：2011-02-03
申请人： Chien-Chih LEE , Wei-Chin Hsu , Hsien-Wen Liu
发明人： Chien-Chih LEE , Wei-Chin Hsu , Hsien-Wen Liu
IPC分类号： H01P1/205
CPC分类号： H01P1/205 , H01P1/2053 , H01P7/04
摘要： A high-order harmonic device of a cavity filter including a base and a lid cover the base is disclosed. The base has a through groove connecting to an upper and a lower portion. The base has a plurality of output terminal with metallic conductor extending into the inner side formed on the surface of the sidewall. The base has resonance space formed indented to receive the metallic conductor and extending to connect to the through groove. The lid has a plurality of threading holes formed corresponding to chambers and partitions received with adjusting elements for height adjustment. The adjusting elements has the resonance bars corresponding to every chamber and the suppressing bars corresponding to every partition. By adjusting suppressing bar and the partition to a predetermined distance, the space of the channel for transmitting the high-order harmonic wave can be reduced to suppress noise produced by high-order harmonic wave.
摘要翻译：公开了一种包括基座和盖子覆盖基座的空腔滤波器的高次谐波装置。基部具有连接到上部和下部的通孔。基座具有多个输出端子，金属导体延伸到形成在侧壁表面上的内侧。底座具有形成为凹入的谐振空间，用于容纳金属导体并延伸以连接到通孔。所述盖具有多个对应于室和隔板形成的穿孔，所述隔间和隔板被接纳有用于高度调节的调节元件。调节元件具有对应于每个室的共振杆和对应于每个分区的抑制棒。通过将抑制棒和隔板调节到预定距离，可以减少用于发送高次谐波的通道的空间，以抑制由高次谐波产生的噪声。

3. 发明授权

US08704614B2 Cavity filter having surge suppress means 失效
标题翻译：具有浪涌抑制装置的腔室滤波器
公开(公告)号：US08704614B2
公开(公告)日：2014-04-22
申请号：US13115702
申请日：2011-05-25
申请人： Hsien-Wen Liu , Chien-Chih Lee , Chin-Hsuan Tsai , Shang-Yu Yang
发明人： Hsien-Wen Liu , Chien-Chih Lee , Chin-Hsuan Tsai , Shang-Yu Yang
IPC分类号： H01P1/213 , H01P1/208 , H01P1/162
CPC分类号： H01P1/2138 , H01P1/30
摘要： A cavity filter includes a base member defining therein a resonant chamber, an antenna port disposed at the center of the resonant chamber, two signal input/output ports respectively disposed at two distal ends of the resonant chamber for signal input/output, a cover member covering the base member, two feedback channels disposed in the base member at two opposite lateral sides relative to the resonant chamber and respectively connected between the signal ports and the antenna port, and wave-absorbing components respectively mounted in the feedback channels for removing surge waves from feedback frequency components in the feedback channels.
摘要翻译：空腔滤波器包括：在其中限定谐振室的基座构件，设置在谐振室中心的天线端口，分别设置在用于信号输入/输出的谐振室的两个远端处的两个信号输入/输出端口，盖构件覆盖基部构件，两个相对于谐振室的两个相对的横向侧设置在基座构件中并且分别连接在信号端口和天线端口之间的反馈通道，以及分别安装在反馈通道中用于去除浪涌波的波浪吸收组件来自反馈信号中的反馈频率分量。

4. 发明授权

US08912595B2 Trench MOS structure and method for forming the same 有权
标题翻译：沟槽MOS结构及其形成方法
公开(公告)号：US08912595B2
公开(公告)日：2014-12-16
申请号：US13106852
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66 , H01L21/308
CPC分类号： H01L29/7813 , H01L21/3083 , H01L29/4236 , H01L29/66666 , H01L29/66734 , H01L29/7827
摘要： A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.
摘要翻译：公开了一种沟槽MOS结构。沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。外延层具有第一导电类型并且设置在第一侧。掺杂阱具有第二导电类型并且设置在外延层上。掺杂区域具有第一导电类型并且被布置在掺杂阱上。沟槽栅极部分地设置在掺杂区域中。沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

5. 发明授权

US08816715B2 MOS test structure, method for forming MOS test structure and method for performing wafer acceptance test 有权
标题翻译： MOS测试结构，用于形成MOS测试结构的方法和用于进行晶片验收测试的方法
公开(公告)号：US08816715B2
公开(公告)日：2014-08-26
申请号：US13105913
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G01R31/02 , G01R31/26 , H01L21/66 , G01R31/28
CPC分类号： H01L22/34 , G01R31/02 , G01R31/26 , G01R31/2644 , G01R31/2831
摘要： A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.
摘要翻译：公开了MOS测试结构。划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。外延层设置在第一侧上，掺杂阱设置在外延层上，并且掺杂区域设置在掺杂阱上。第一深度的沟槽栅极设置在掺杂区域，掺杂阱和划线区域中。导电材料填充测试，通过该测试具有覆盖测试通孔的内壁的第二深度和隔离，并且设置在掺杂区域，掺杂阱，外延层和划线区域中，以电连接到外延层，使得测试通孔能够一起测试外延层和衬底。

6. 发明授权

US08807429B2 Recognition system having periodic guided-wave structure 有权
标题翻译：识别系统具有周期性导波结构
公开(公告)号：US08807429B2
公开(公告)日：2014-08-19
申请号：US13525310
申请日：2012-06-16
申请人： Hsien-Wen Liu
发明人： Hsien-Wen Liu
IPC分类号： G06Q90/00
CPC分类号： G06K19/07786 , H01Q1/2216 , H04B5/0062 , H04B7/10
摘要： A recognition system is offered. The recognition system is for sensing a plurality of units under test of at least an object under test. The recognition system comprises a periodic guided-wave structure and a near field sensing device. The periodic guided-wave structure is disposed under the object under test and has a plurality of conductive units periodically arranged on a plane. The near field sensing device has a near field antenna and senses the plurality of units under test through detecting the near field magnetic field. The periodic guided-wave structure confines the electromagnetic field for facilitating to determine the distance from any one of the units under test to the periodic guided-wave structure.
摘要翻译：提供识别系统。识别系统用于感测至少被测物体被测试的多个单元。识别系统包括周期性导波结构和近场感测装置。周期性导波结构设置在被测物体的下方，并且具有周期性地布置在平面上的多个导电单元。近场感测装置具有近场天线，并且通过检测近场磁场来感测被测试的多个单元。周期导波结构限制电磁场，以便于确定从被测单元中的任一个到周期性导波结构的距离。

7. 发明授权

US08692318B2 Trench MOS structure and method for making the same 有权
标题翻译：沟槽MOS结构和制作方法
公开(公告)号：US08692318B2
公开(公告)日：2014-04-08
申请号：US13104924
申请日：2011-05-10
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0649 , H01L29/0696 , H01L29/1095 , H01L29/66734
摘要： A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.
摘要翻译：提供沟槽MOS结构。沟槽MOS结构包括保护环内的衬底，外延层，沟槽，栅极隔离，沟槽栅极，保护环和加强结构。衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。外延层具有第一导电类型并且设置在第一侧。沟槽设置在外延层中。栅极隔离覆盖沟槽的内壁。沟槽栅设置在沟槽中并且具有第一导电类型。保护环具有第二导电类型并且设置在外延层内。加强结构具有电绝缘材料并且设置在保护环内。

8. 发明授权

US08458842B2 Post-CMP wafer cleaning apparatus 有权
标题翻译： CMP后晶圆清洗装置
公开(公告)号：US08458842B2
公开(公告)日：2013-06-11
申请号：US13104964
申请日：2011-05-10
申请人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B08B3/02
CPC分类号： H01L21/67051 , H01L21/02052 , H01L21/67046
摘要： A post-CMP wafer cleaning apparatus includes a chamber; a plurality of rollers adapted to hold and rotate a wafer within the chamber; at least one brush adapted to scrub a surface of the wafer to be cleaned; and a liquid spraying device adapted to spray a liquid on the wafer, the liquid spraying device comprising two spray bars jointed together via a joint member.
摘要翻译： CMP后晶片清洗装置包括：腔室; 多个辊子，适于在所述腔室内保持和旋转晶片; 至少一个刷子，适于擦拭要清洁的晶片的表面; 以及适于将液体喷射在晶片上的液体喷射装置，所述液体喷射装置包括通过接头构件连接在一起的两个喷射杆。

9. 发明授权

US08431933B2 Memory layout structure and memory structure 有权
标题翻译：内存布局结构和内存结构
公开(公告)号：US08431933B2
公开(公告)日：2013-04-30
申请号：US12874232
申请日：2010-09-02
申请人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
发明人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
IPC分类号： H01L29/10
CPC分类号： H01L29/4983 , H01L27/0207 , H01L27/10855 , H01L27/10876 , H01L27/10882 , H01L29/4236
摘要： A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.
摘要翻译：公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸（边缘壁），以执行侧壁接触。自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

10. 发明授权

US08394721B2 Method for obtaining a layout design for an existing integrated circuit 有权
标题翻译：获得现有集成电路布局设计的方法
公开(公告)号：US08394721B2
公开(公告)日：2013-03-12
申请号：US13104986
申请日：2011-05-11
申请人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/311
CPC分类号： H01L27/0203 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.
摘要翻译：一种用于获得现有集成电路的布局设计的方法，其中集成电路管芯以倾斜角抛光以形成倾斜的抛光表面，并且获得倾斜抛光表面的一个或多个图像。图像可以直接重叠，或者图像或图像可以用于提供信息以获得包括布局结构的至少一个重复单元结构的布局设计。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式