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1. 发明申请

US20050275043A1 Novel semiconductor device design 审中-公开
标题翻译：新型半导体器件设计
公开(公告)号：US20050275043A1
公开(公告)日：2005-12-15
申请号：US11146692
申请日：2005-06-07
申请人： Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Cheng-Chuan Huang , Tong-Heuan Chung
发明人： Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Cheng-Chuan Huang , Tong-Heuan Chung
IPC分类号： H01L21/768 , H01L27/02 , H01L29/76
CPC分类号： H01L21/76838 , H01L21/76895 , H01L27/0207
摘要： An integrated circuit having small layout area and a method of forming the same are provided. A slant contact is formed by shifting a portion of a contact a distance less than a whole dimension of the contact along the direction shifted. By using slant contacts, the optical proximity effect is reduced, the device density in the integrated circuit is increased and cross talk is reduced. In the preferred embodiment, the slant contact is combined with other techniques such as compound interconnection, butted local interconnection and slim spacers to reduce the layout area. In another embodiments, a six-transistor SRAM cell can be designed with a slant contact, compound interconnection and butted local interconnection to reduce the layout area.
摘要翻译：提供了具有小布局面积的集成电路及其形成方法。通过使触点的一部分沿着移动的方向移动小于接触件的整个尺寸的距离来形成倾斜接触。通过使用倾斜触点，光学邻近效应降低，集成电路中的器件密度增加并且串扰减少。在优选实施例中，倾斜触点与诸如复合互连，对接的局部互连和细长间隔物的其它技术组合以减少布局面积。在另一个实施例中，可以设计六晶体管SRAM单元，其具有倾斜接触，复合互连和对接的局部互连以减小布局面积。

2. 发明申请

US20070075356A1 Strained silicon device 有权
标题翻译：应变硅器件
公开(公告)号：US20070075356A1
公开(公告)日：2007-04-05
申请号：US11549002
申请日：2006-10-12
申请人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7843 , H01L29/78621
摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.
摘要翻译：微电子器件的制造方法包括通过在衬底上形成多晶硅栅极结构并在衬底中形成轻掺杂的源极/漏极区，在硅衬底上形成p沟道晶体管。邻近多晶硅栅极结构的相对侧壁形成氧化物衬垫和氮化物间隔物，并且在氧化物衬垫的相对侧上的半导体衬底中蚀刻凹陷。在氧化物衬垫的两侧形成升高的SiGe源极/漏极区，并且在氧化物衬垫上形成细长的间隔物。在形成升高的SiGe源极/漏极区域期间，使用多晶硅栅极结构上的硬掩模来保护多晶硅栅极结构。然后将源极/漏极掺杂剂注入到包括SiGe区域的衬底中。

3. 发明授权

US07135372B2 Strained silicon device manufacturing method 有权
公开(公告)号：US07135372B2
公开(公告)日：2006-11-14
申请号：US10937722
申请日：2004-09-09
申请人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7843 , H01L29/78621
摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

4. 发明申请

US20060003520A1 Method for forming semiconductor device with modified channel compressive stress 有权
标题翻译：用于形成具有改变的通道压应力的半导体器件的方法
公开(公告)号：US20060003520A1
公开(公告)日：2006-01-05
申请号：US11219439
申请日：2005-09-02
申请人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L21/8238
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for forming a semiconductor device provides for forming a gate region on top of a substrate. Gate sidewall liners are formed on opposed sides of the gate region, the sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. Recessed spacers are formed on top of the sidewall liners. The sidewall liner underneath the spacers is pulled back from the edge of the respective spacer by a predetermined distance. The recessed spacers are formed by reducing the height of the originally formed spacer. The height of the spacers is lower than a height of the gate sidewall liner and the width of the horizontal part of the sidewall liner is shorter than the width of the spacer. The reduced spacer height reduces device channel stress.
摘要翻译：用于形成半导体器件的方法提供在衬底的顶部上形成栅极区域。栅极侧壁衬里形成在栅极区域的相对侧上，侧壁衬里具有接触栅极区域的侧壁和与衬底接触的水平部分的垂直部分。嵌入式间隔件形成在侧壁衬套的顶部。垫片下方的侧壁衬套从相应的垫片的边缘被拉回预定的距离。通过减小原来形成的间隔物的高度来形成凹进的间隔物。间隔件的高度低于门侧壁衬套的高度，并且侧壁衬套的水平部分的宽度比间隔件的宽度短。减少的间隔物高度降低了设备通道应力。

5. 发明授权

US06975006B2 Semiconductor device with modified channel compressive stress 失效
标题翻译：具有改变通道压应力的半导体器件
公开(公告)号：US06975006B2
公开(公告)日：2005-12-13
申请号：US10627849
申请日：2003-07-25
申请人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L29/49 , H01L31/119
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device includes a substrate and a gate region on top of a substrate. First and second gate sidewall liners are situated on first and second sides of the gate region respectively, the first and second sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. First and second recessed spacers are situated on top of the first and second sidewall liners respectively. The height of the first and second spacers is lower than the height of the gate sidewall liner whereas the width of the horizontal part of the sidewall liner is shorter than the width of the spacer.
摘要翻译：半导体器件包括衬底和位于衬底顶部上的栅极区域。第一和第二栅极侧壁衬里分别位于栅极区域的第一和第二侧上，第一和第二侧壁衬里具有接触栅极区域的侧壁和接触衬底的水平部分的垂直部分。第一和第二凹陷垫片分别位于第一和第二侧壁衬里的顶部上。第一和第二间隔件的高度低于栅极侧壁衬套的高度，而侧壁衬套的水平部分的宽度比间隔件的宽度短。

6. 发明授权

US08569845B2 Strained silicon device 有权
标题翻译：应变硅器件
公开(公告)号：US08569845B2
公开(公告)日：2013-10-29
申请号：US11549002
申请日：2006-10-12
申请人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L21/02
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7843 , H01L29/78621
摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.
摘要翻译：微电子器件的制造方法包括通过在衬底上形成多晶硅栅极结构并在衬底中形成轻掺杂的源极/漏极区，在硅衬底上形成p沟道晶体管。邻近多晶硅栅极结构的相对侧壁形成氧化物衬垫和氮化物间隔物，并且在氧化物衬垫的相对侧上的半导体衬底中蚀刻凹陷。在氧化物衬垫的两侧形成升高的SiGe源极/漏极区，并且在氧化物衬垫上形成细长的间隔物。在形成升高的SiGe源极/漏极区域期间，使用多晶硅栅极结构上的硬掩模来保护多晶硅栅极结构。然后将源极/漏极掺杂剂注入到包括SiGe区域的衬底中。

7. 发明授权

US07462554B2 Method for forming semiconductor device with modified channel compressive stress 有权
标题翻译：用于形成具有改变的通道压应力的半导体器件的方法
公开(公告)号：US07462554B2
公开(公告)日：2008-12-09
申请号：US11219439
申请日：2005-09-02
申请人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L31/119
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for forming a semiconductor device provides for forming a gate region on top of a substrate. Gate sidewall liners are formed on opposed sides of the gate region, the sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. Recessed spacers are formed on top of the sidewall liners. The sidewall liner underneath the spacers is pulled back from the edge of the respective spacer by a predetermined distance. The recessed spacers are formed by reducing the height of the originally formed spacer. The height of the spacers is lower than a height of the gate sidewall liner and the width of the horizontal part of the sidewall liner is shorter than the width of the spacer. The reduced spacer height reduces device channel stress.
摘要翻译：用于形成半导体器件的方法提供在衬底的顶部上形成栅极区域。栅极侧壁衬里形成在栅极区域的相对侧上，侧壁衬里具有接触栅极区域的侧壁和与衬底接触的水平部分的垂直部分。嵌入式间隔件形成在侧壁衬垫的顶部。垫片下方的侧壁衬套从相应的垫片的边缘被拉回预定的距离。通过减小原来形成的间隔物的高度来形成凹进的间隔物。间隔件的高度低于门侧壁衬套的高度，并且侧壁衬套的水平部分的宽度比间隔件的宽度短。减少的间隔物高度降低了设备通道应力。

8. 发明申请

US20050019998A1 Semiconductor device with modified channel compressive stress and the method for making same 失效
标题翻译：具有改进的通道压应力的半导体器件及其制造方法
公开(公告)号：US20050019998A1
公开(公告)日：2005-01-27
申请号：US10627849
申请日：2003-07-25
申请人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L29/49 , H01L21/336
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device and the method for making same is disclosed. The semiconductor device has a substrate and a gate region on top of the substrate. It further has a first and second gate sidewall liners situated on a first and second sides of the gate region respectively, the first and second sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate; and a first and second recessed spacers situated on top of the first and second sidewall liners respectively, wherein a height of the first and second spacers is lower than a height of the gate sidewall liner and wherein the width of the horizontal part of the sidewall liner is shorter than the width of the spacer.
摘要翻译：公开了一种半导体器件及其制造方法。半导体器件在衬底的顶部具有衬底和栅极区域。其还具有分别位于栅极区域的第一和第二侧上的第一和第二栅极侧壁衬里，第一和第二侧壁衬里具有接触栅极区域的侧壁和与衬底接触的水平部分的垂直部分; 以及分别位于第一和第二侧壁衬套的顶部上的第一和第二凹槽，其中第一和第二间隔件的高度低于门侧壁衬套的高度，并且其中侧壁衬套的水平部分的宽度比间隔件的宽度短。

9. 发明申请

US20060051922A1 Strained silicon device manufacturing method 有权
标题翻译：应变硅器件制造方法
公开(公告)号：US20060051922A1
公开(公告)日：2006-03-09
申请号：US10937722
申请日：2004-09-09
申请人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7843 , H01L29/78621
摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.
摘要翻译：微电子器件的制造方法包括通过在衬底上形成多晶硅栅极结构并在衬底中形成轻掺杂的源极/漏极区，在硅衬底上形成p沟道晶体管。邻近多晶硅栅极结构的相对侧壁形成氧化物衬垫和氮化物间隔物，并且在氧化物衬垫的相对侧上的半导体衬底中蚀刻凹陷。在氧化物衬垫的两侧形成升高的SiGe源极/漏极区，并且在氧化物衬垫上形成细长的间隔物。在形成升高的SiGe源极/漏极区域期间，使用多晶硅栅极结构上的硬掩模来保护多晶硅栅极结构。然后将源极/漏极掺杂剂注入到包括SiGe区域的衬底中。

10. 发明申请

US20080171419A1 Method for forming SOI device 有权
标题翻译： SOI器件形成方法
公开(公告)号：US20080171419A1
公开(公告)日：2008-07-17
申请号：US11652624
申请日：2007-01-12
申请人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
IPC分类号： H01L21/76 , H01L21/44
CPC分类号： H01L29/78603 , H01L21/743 , H01L21/76283 , H01L21/84 , H01L29/66772 , H01L29/785
摘要： A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.
摘要翻译：提供了一种用于在绝缘体上硅（SOI）晶片上形成衬底接触的方法，其可以与在SOI晶片切割之后不进行额外处理的SOI器件的工艺集成。该方法可应用于许多较先进的封装技术，例如倒装芯片和芯片堆叠，通过切割的SOI晶片的正面直接产生与硅衬底的接触。

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