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1. 发明授权

US08633549B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08633549B2
公开(公告)日：2014-01-21
申请号：US13267068
申请日：2011-10-06
申请人： Chieh-Te Chen , Shih-Fang Tzou , Jiunn-Hsiung Liao , Yi-Po Lin
发明人： Chieh-Te Chen , Shih-Fang Tzou , Jiunn-Hsiung Liao , Yi-Po Lin
IPC分类号： H01L27/11 , H01L21/8234 , H01L21/8244
CPC分类号： H01L21/28079 , H01L21/027 , H01L21/3212 , H01L21/32139 , H01L21/8232 , H01L27/0629
摘要： A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.
摘要翻译：半导体器件包括金属栅电极，无源器件和硬掩模层。无源器件具有多晶硅元件层。硬掩模层设置在金属栅电极和无源电极上，并且具有彼此基本共面的第一开口和第二开口，其中金属栅极电极和多晶硅元件层分别经由第一开口暴露，第二个开口并且第一开口和金属栅电极之间的距离基本上小于第二开口和多晶硅元件层之间的距离。

2. 发明申请

US20130087861A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130087861A1
公开(公告)日：2013-04-11
申请号：US13267068
申请日：2011-10-06
申请人： Chieh-Te CHEN , Shih-Fang Tzou , Jiunn-Hsiung Liao , Yi-Po Lin
发明人： Chieh-Te CHEN , Shih-Fang Tzou , Jiunn-Hsiung Liao , Yi-Po Lin
IPC分类号： H01L27/10 , H01L21/8234
CPC分类号： H01L21/28079 , H01L21/027 , H01L21/3212 , H01L21/32139 , H01L21/8232 , H01L27/0629
摘要： A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.
摘要翻译：半导体器件包括金属栅电极，无源器件和硬掩模层。无源器件具有多晶硅元件层。硬掩模层设置在金属栅电极和无源电极上，并且具有彼此基本共面的第一开口和第二开口，其中金属栅极电极和多晶硅元件层分别经由第一开口暴露，第二个开口并且第一开口和金属栅电极之间的距离基本上小于第二开口和多晶硅元件层之间的距离。

3. 发明申请

US20120264279A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120264279A1
公开(公告)日：2012-10-18
申请号：US13085787
申请日：2011-04-13
申请人： Shui-Yen LU , Yi-Po Lin , Jiunn-Hsiung Liao , Shih-Fang Tzou , Shin-Chin Chen
发明人： Shui-Yen LU , Yi-Po Lin , Jiunn-Hsiung Liao , Shih-Fang Tzou , Shin-Chin Chen
IPC分类号： H01L21/28
CPC分类号： H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method for fabricating a semiconductor device, wherein the method comprises steps as follows: a semiconductor structure comprising a substrate, a dummy gate structure having a dielectric layer disposed over the substrate and a silicon layer disposed over the dielectric layer, and an etching stop layer (ESL) and an inter-layer dielectric (ILD) layer both of which are sequentially disposed over the substrate and the dummy gate structure is first provided. Then, a chemical mechanical polishing (CMP) is performed to planrizing the ILD layer and expose the ESL. Subsequently, an in-situ etching process is conducted to remove portions of the ESL and the silicon layer to form an opening in the dummy gate structure. Next, metal material is filled into the opening.
摘要翻译：一种制造半导体器件的方法，其中所述方法包括以下步骤：包括衬底的半导体结构，设置在所述衬底上的电介质层的伪栅极结构和设置在所述电介质层上的硅层，以及蚀刻停止层（ESL）和层间电介质（ILD）层，它们都顺序地设置在衬底上，并且首先提供虚拟栅极结构。然后，进行化学机械抛光（CMP）以平整ILD层并暴露ESL。随后，进行原位蚀刻工艺以去除ESL和硅层的部分以在虚拟栅极结构中形成开口。接下来，将金属材料填充到开口中。

4. 发明申请

US20100105205A1 CLEANING SOLUTION AND SEMICONDCUTOR PROCESS USING THE SAME 审中-公开
标题翻译：使用相同的清洁溶液和半导体工艺
公开(公告)号：US20100105205A1
公开(公告)日：2010-04-29
申请号：US12259033
申请日：2008-10-27
申请人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L21/44 , C11D3/28
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/3281 , H01L21/02063 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water.
摘要翻译：提供半导体工艺。首先，在基板上依次形成金属层，电介质层和图案化的硬掩模层。此后，去除介电层的一部分以形成露出金属层的开口。之后，使用清洁溶液清洁开口。清洗液含有含量为0.00275〜3重量％的三唑化合物，含量为1〜10重量％的硫酸，含量为1〜200ppm的氢氟酸和水。

5. 发明申请

US20080064176A1 Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device 有权
标题翻译：去除间隔物的方法，制造金属氧化物半导体晶体管器件的方法和金属氧化物半导体晶体管器件
公开(公告)号：US20080064176A1
公开(公告)日：2008-03-13
申请号：US11531260
申请日：2006-09-12
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.
摘要翻译：一种去除间隔物的方法，制造金属氧化物半导体晶体管器件的方法和金属氧化物半导体晶体管器件，其中在去除间隔物之前，保护层沉积在间隔物上形成在源极/漏极区域上的材料层（例如自对准硅化物层）和栅电极，使得隔离物上的保护层的厚度小于材料层上的厚度，然后保护层部分去除，使得隔离物上的保护层的厚度近似为零，并且保护层的一部分保留在材料层上。因此，当去除间隔物时，材料层可被保护层保护。

6. 发明申请

US20070238238A1 CMOS device and fabricating method thereof 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US20070238238A1
公开(公告)日：2007-10-11
申请号：US11389617
申请日：2006-03-24
申请人： Shih-Wei Sun , Shih-Fang Tzou , Jiunn-Hsiung Liao , Pei-Yu Chou
发明人： Shih-Wei Sun , Shih-Fang Tzou , Jiunn-Hsiung Liao , Pei-Yu Chou
IPC分类号： H01L21/8238 , H01L29/80
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/7843
摘要： A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation structure. Further, the first-type MOS transistor is disposed on the first active area of the substrate, and the second-type MOS transistor is disposed on the second active area of the substrate. The first stress layer is compliantly disposed on the first-type MOS transistor of the first active area. The first liner layer is compliantly disposed on the first stress layer. The second stress layer is compliantly disposed on the second-type MOS transistor of the second active area.
摘要翻译：提供一种CMOS器件，包括衬底，第一类型MOS晶体管，第二类型MOS晶体管，第一应力层，第一衬里层和第二应力层。衬底具有由隔离结构隔开的第一有源区和第二有源区。此外，第一型MOS晶体管设置在衬底的第一有源区上，并且第二型MOS晶体管设置在衬底的第二有源区上。第一应力层顺应地设置在第一有源区的第一型MOS晶体管上。第一衬里层顺应地设置在第一应力层上。第二应力层顺从地设置在第二有源区的第二型MOS晶体管上。

7. 发明申请

US20080191287A1 METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR 有权
标题翻译：制备应变硅CMOS晶体管的方法
公开(公告)号：US20080191287A1
公开(公告)日：2008-08-14
申请号：US11674660
申请日：2007-02-13
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.
摘要翻译：首先，提供具有第一有源区和第二有源区的半导体基板。第一有源区包括第一晶体管，第二有源区包括第二晶体管。第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

8. 发明申请

US20080150041A1 Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device 审中-公开
公开(公告)号：US20080150041A1
公开(公告)日：2008-06-26
申请号：US12042345
申请日：2008-03-05
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L29/78
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

9. 发明申请

US20110076814A1 METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR 有权
标题翻译：制备应变硅CMOS晶体管的方法
公开(公告)号：US20110076814A1
公开(公告)日：2011-03-31
申请号：US12959393
申请日：2010-12-03
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.
摘要翻译：首先，提供具有第一有源区和第二有源区的半导体基板。第一有源区包括第一晶体管，第二有源区包括第二晶体管。第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

10. 发明申请

US20110068408A1 STRAINED-SILICON CMOS TRANSISTOR 审中-公开
标题翻译：应变硅CMOS晶体管
公开(公告)号：US20110068408A1
公开(公告)日：2011-03-24
申请号：US12959399
申请日：2010-12-03
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained-silicon CMOS transistor includes: a semiconductor substrate having a first active region, a second active region, and an isolation structure disposed between the first active region and the second active region; a first transistor, disposed on the first active region; a second transistor, disposed on the second active region; a first etching stop layer, disposed on the first transistor and the second transistor; a first stress layer, disposed on the first transistor; a second etching stop layer, disposed on the first transistor and the first stress layer, wherein an edge of the first stress layer is aligned with that of the second etching stop layer; a second stress layer, disposed on the second transistor; and a third etching stop layer disposed on the second transistor and the second stress layer, wherein an edge of the second stress layer is aligned with that of the third etching stop layer.
摘要翻译：应变硅CMOS晶体管包括：具有第一有源区，第二有源区和设置在第一有源区和第二有源区之间的隔离结构的半导体衬底; 第一晶体管，设置在第一有源区上; 第二晶体管，设置在第二有源区上; 第一蚀刻停止层，设置在第一晶体管和第二晶体管上; 第一应力层，设置在所述第一晶体管上; 第二蚀刻停止层，设置在第一晶体管和第一应力层上，其中第一应力层的边缘与第二蚀刻停止层的边缘对准; 第二应力层，设置在所述第二晶体管上; 以及设置在所述第二晶体管和所述第二应力层上的第三蚀刻停止层，其中所述第二应力层的边缘与所述第三蚀刻停止层的边缘对准。

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