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1. 发明申请

US20100105205A1 CLEANING SOLUTION AND SEMICONDCUTOR PROCESS USING THE SAME 审中-公开
标题翻译：使用相同的清洁溶液和半导体工艺
公开(公告)号：US20100105205A1
公开(公告)日：2010-04-29
申请号：US12259033
申请日：2008-10-27
申请人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L21/44 , C11D3/28
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/3281 , H01L21/02063 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water.
摘要翻译：提供半导体工艺。首先，在基板上依次形成金属层，电介质层和图案化的硬掩模层。此后，去除介电层的一部分以形成露出金属层的开口。之后，使用清洁溶液清洁开口。清洗液含有含量为0.00275〜3重量％的三唑化合物，含量为1〜10重量％的硫酸，含量为1〜200ppm的氢氟酸和水。

2. 发明授权

US08137472B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08137472B2
公开(公告)日：2012-03-20
申请号：US13161659
申请日：2011-06-16
申请人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L21/302
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/3281 , H01L21/02063 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.
摘要翻译：提供半导体工艺。首先，在基板上依次形成金属层，电介质层和图案化的硬掩模层。此后，去除介电层的一部分以形成露出金属层的开口。之后，使用清洁溶液清洁开口。清洗液含有含量为0.00275〜3重量％的三唑化合物，含量为1〜10重量％的硫酸，含量为1〜200ppm的氢氟酸和水。半导体工艺可以降低不完全打开，泄漏或短路的可能性，从而提高产品的产量。

3. 发明申请

US20110244678A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20110244678A1
公开(公告)日：2011-10-06
申请号：US13161659
申请日：2011-06-16
申请人： Chang-Hsiao LEE , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chang-Hsiao LEE , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L21/283
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/3281 , H01L21/02063 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.
摘要翻译：提供半导体工艺。首先，在基板上依次形成金属层，电介质层和图案化的硬掩模层。此后，去除介电层的一部分以形成露出金属层的开口。之后，使用清洁溶液清洁开口。清洗液含有含量为0.00275〜3重量％的三唑化合物，含量为1〜10重量％的硫酸，含量为1〜200ppm的氢氟酸和水。半导体工艺可以降低不完全打开，泄漏或短路的可能性，从而提高产品的产量。

4. 发明申请

US20110130008A1 METHOD TO CONTROL CRITICAL DIMENSION 审中-公开
标题翻译：控制关键尺寸的方法
公开(公告)号：US20110130008A1
公开(公告)日：2011-06-02
申请号：US12629031
申请日：2009-12-01
申请人： Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L21/306
CPC分类号： H01L21/0332 , G03F7/0752 , G03F7/094 , H01L21/0274
摘要： A method to control a critical dimension is disclosed. First, a material layer and a composite patterned layer covering the material layer are provided. The composite patterned layer has a pattern defining a first critical dimension. Later, an etching gas is used to perform an etching step to etch the composite patterned layer and a pattern-transferring step is carried out so that thereby the underlying material layer has a transferred pattern with a second critical dimension which is substantially smaller than the first critical dimension.
摘要翻译：公开了一种控制临界尺寸的方法。首先，提供覆盖材料层的材料层和复合图案层。复合图案层具有限定第一临界尺寸的图案。之后，使用蚀刻气体来进行蚀刻步骤以蚀刻复合图案化层，并执行图案转印步骤，使得下面的材料层具有转移图案，其具有基本上小于第一临界尺寸的第二临界尺寸关键维度。

5. 发明申请

US20090142931A1 Cleaning method following opening etch 有权
标题翻译：打开蚀刻后的清洁方法
公开(公告)号：US20090142931A1
公开(公告)日：2009-06-04
申请号：US11946875
申请日：2007-11-29
申请人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： H01L21/461 , C23F1/12
CPC分类号： H01L21/02063 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment process is performed to clean polymer residues having carbon-fluorine (C—F) bonds remained in the opening. Finally, a wet cleaning process is performed.
摘要翻译：提供了开口蚀刻后的清洁方法。首先，提供具有电介质层的半导体基板。硬掩模层至少包括金属层。然后进行开口蚀刻以形成电介质层中的至少一个开口。进行氮（N2）处理工艺以清洁残留在开口中的具有碳 - 氟（C-F）键的聚合物残基。最后，进行湿式清洗处理。

6. 发明授权

US08080877B2 Damascene interconnection structure and dual damascene process thereof 有权
标题翻译：大马士革互连结构及其双镶嵌工艺
公开(公告)号：US08080877B2
公开(公告)日：2011-12-20
申请号：US12821136
申请日：2010-06-23
申请人： Chun-Jen Huang , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chun-Jen Huang , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译：公开了一种双镶嵌工艺。提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。介电层沉积在盖层上。氧化硅层沉积在电介质层上。在氧化硅层上形成金属硬掩模。将沟槽开口蚀刻到金属硬掩模中。部分通孔特征被蚀刻到沟槽开口内的电介质层中。沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。

7. 发明申请

US20100258941A1 DAMASCENE INTERCONNECTION STRUCTURE AND DUAL DAMASCENE PROCESS THEREOF 有权
标题翻译：大连互连结构及其双重破坏过程
公开(公告)号：US20100258941A1
公开(公告)日：2010-10-14
申请号：US12821136
申请日：2010-06-23
申请人： Chun-Jen Huang , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chun-Jen Huang , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L23/532
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译：公开了一种双镶嵌工艺。提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。介电层沉积在盖层上。氧化硅层沉积在电介质层上。在氧化硅层上形成金属硬掩模。将沟槽开口蚀刻到金属硬掩模中。部分通孔特征被蚀刻到沟槽开口内的电介质层中。沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。

8. 发明申请

US20080171433A1 DAMASCENE INTERCONNECTION STRUCTURE AND DUAL DAMASCENE PROCESS THEREOF 有权
标题翻译：大连互连结构及其双重破坏过程
公开(公告)号：US20080171433A1
公开(公告)日：2008-07-17
申请号：US11621996
申请日：2007-01-11
申请人： Chun-Jen Huang , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chun-Jen Huang , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L21/768
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译：公开了一种双镶嵌工艺。提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。介电层沉积在盖层上。氧化硅层沉积在电介质层上。在氧化硅层上形成金属硬掩模。将沟槽开口蚀刻到金属硬掩模中。部分通孔特征被蚀刻到沟槽开口内的电介质层中。沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。执行衬垫去除步骤以通过使用CF 4 N 3 N 3等离子体从双镶嵌开口选择性地去除暴露的盖层。

9. 发明申请

US20080146036A1 Semiconductor manufacturing process 有权
标题翻译：半导体制造工艺
公开(公告)号：US20080146036A1
公开(公告)日：2008-06-19
申请号：US11611890
申请日：2006-12-18
申请人： Yu-Tsung Lai , Chun-Jen Huang , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Yu-Tsung Lai , Chun-Jen Huang , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L21/3065
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/76811 , H01L21/76814 , Y10S438/906 , Y10S438/963
摘要： Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.
摘要翻译：公开了一种半导体制造方法，其中使用含氟自由基的等离子体来蚀刻硬掩模和其下面的层; 并且使用与氟自由基反应的气体与残留的氟自由基反应来进行处理以形成含氟化合物并将其除去。因此，可以避免通过存在于硬掩模中的氟自由基和钛成分的反应形成的沉淀物引起工艺缺陷。

10. 发明授权

US08282842B2 Cleaning method following opening etch 有权
标题翻译：打开蚀刻后的清洁方法
公开(公告)号：US08282842B2
公开(公告)日：2012-10-09
申请号：US11946875
申请日：2007-11-29
申请人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： H01B13/00
CPC分类号： H01L21/02063 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment process is performed to clean polymer residues having carbon-fluorine (C—F) bonds remained in the opening. Finally, a wet cleaning process is performed.
摘要翻译：提供了开口蚀刻后的清洁方法。首先，提供具有电介质层的半导体基板。硬掩模层至少包括金属层。然后进行开口蚀刻以形成电介质层中的至少一个开口。进行氮（N2）处理工艺以清洁残留在开口中的具有碳 - 氟（C-F）键的聚合物残基。最后，进行湿式清洗处理。

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