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1. 发明授权

US08633549B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08633549B2
公开(公告)日：2014-01-21
申请号：US13267068
申请日：2011-10-06
申请人： Chieh-Te Chen , Shih-Fang Tzou , Jiunn-Hsiung Liao , Yi-Po Lin
发明人： Chieh-Te Chen , Shih-Fang Tzou , Jiunn-Hsiung Liao , Yi-Po Lin
IPC分类号： H01L27/11 , H01L21/8234 , H01L21/8244
CPC分类号： H01L21/28079 , H01L21/027 , H01L21/3212 , H01L21/32139 , H01L21/8232 , H01L27/0629
摘要： A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.
摘要翻译：半导体器件包括金属栅电极，无源器件和硬掩模层。无源器件具有多晶硅元件层。硬掩模层设置在金属栅电极和无源电极上，并且具有彼此基本共面的第一开口和第二开口，其中金属栅极电极和多晶硅元件层分别经由第一开口暴露，第二个开口并且第一开口和金属栅电极之间的距离基本上小于第二开口和多晶硅元件层之间的距离。

2. 发明申请

US20130109151A1 METHOD FOR FORMING VOID-FREE DIELECTRIC LAYER 有权
标题翻译：形成无电介质层的方法
公开(公告)号：US20130109151A1
公开(公告)日：2013-05-02
申请号：US13281459
申请日：2011-10-26
申请人： Ching-Pin Hsu , Yi-Po Lin , Jiunn-Hsiung Liao , Chieh-Te Chen , Feng-Yi Chang , Shang-Yuan Tsai , Li-Chiang Chen
发明人： Ching-Pin Hsu , Yi-Po Lin , Jiunn-Hsiung Liao , Chieh-Te Chen , Feng-Yi Chang , Shang-Yuan Tsai , Li-Chiang Chen
IPC分类号： H01L21/762
CPC分类号： H01L21/76232
摘要： A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.
摘要翻译：公开了一种形成没有空隙的电介质层的方法。首先，提供基板，包括凹部的第一应力层，设置在第一应力层上并覆盖凹部的第二应力层和嵌入凹部中的图案化光致抗蚀剂。第二，执行第一蚀刻步骤以完全去除光致抗蚀剂，使得剩余的第二应力层形成邻近凹部的至少一个突起。然后，在不暴露的情况下形成修整光致抗蚀剂以填充凹部并覆盖突起。然后，进行修整蚀刻步骤以消除突起并且顺利地移除修整光致抗蚀剂。

3. 发明授权

US09196524B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US09196524B2
公开(公告)日：2015-11-24
申请号：US13609213
申请日：2012-09-10
申请人： Chieh-Te Chen , Yi-Po Lin , Jiunn-Hsiung Liao , Feng-Yi Chang , Shang-Yuan Tsai
发明人： Chieh-Te Chen , Yi-Po Lin , Jiunn-Hsiung Liao , Feng-Yi Chang , Shang-Yuan Tsai
IPC分类号： H01L21/336 , H01L21/768 , H01L21/311
CPC分类号： H01L21/76816 , H01L21/31144 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method of a semiconductor device is disclosed in the present invention. First, at least one gate structure and plurality of source/drain regions on a substrate are formed, a dielectric layer is then formed on the substrate, a first contact hole and a second contact hole are formed in the dielectric layer, respectively on the gate structure and the source/drain region, and a third contact hole is formed in the dielectric layer, wherein the third contact hole overlaps the first contact hole and the second contact hole.
摘要翻译：在本发明中公开了一种半导体器件的制造方法。首先，在衬底上形成至少一个栅极结构和多个源极/漏极区域，然后在衬底上形成电介质层，在电介质层中分别在栅极上形成第一接触孔和第二接触孔结构和源极/漏极区，以及在电介质层中形成第三接触孔，其中第三接触孔与第一接触孔和第二接触孔重叠。

4. 发明授权

US08691659B2 Method for forming void-free dielectric layer 有权
标题翻译：无空隙电介质层形成方法
公开(公告)号：US08691659B2
公开(公告)日：2014-04-08
申请号：US13281459
申请日：2011-10-26
申请人： Ching-Pin Hsu , Yi-Po Lin , Jiunn-Hsiung Liao , Chieh-Te Chen , Feng-Yi Chang , Shang-Yuan Tsai , Li-Chiang Chen
发明人： Ching-Pin Hsu , Yi-Po Lin , Jiunn-Hsiung Liao , Chieh-Te Chen , Feng-Yi Chang , Shang-Yuan Tsai , Li-Chiang Chen
IPC分类号： H01L21/762
CPC分类号： H01L21/76232
摘要： A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.
摘要翻译：公开了一种形成没有空隙的电介质层的方法。首先，提供基板，包括凹部的第一应力层，设置在第一应力层上并覆盖凹部的第二应力层和嵌入凹部中的图案化光致抗蚀剂。第二，执行第一蚀刻步骤以完全去除光致抗蚀剂，使得剩余的第二应力层形成邻近凹部的至少一个突起。然后，在不暴露的情况下形成修整光致抗蚀剂以填充凹部并覆盖突起。然后，进行修整蚀刻步骤以消除突起并且顺利地移除修整光致抗蚀剂。

5. 发明申请

US20140073104A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20140073104A1
公开(公告)日：2014-03-13
申请号：US13609213
申请日：2012-09-10
申请人： Chieh-Te Chen , Yi-Po Lin , Jiunn-Hsiung Liao , Feng-Yi Chang , Shang-Yuan Tsai
发明人： Chieh-Te Chen , Yi-Po Lin , Jiunn-Hsiung Liao , Feng-Yi Chang , Shang-Yuan Tsai
IPC分类号： H01L21/336
CPC分类号： H01L21/76816 , H01L21/31144 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method of a semiconductor device is disclosed in the present invention. First, at least one gate structure and plurality of source/drain regions on a substrate are formed, a dielectric layer is then formed on the substrate, a first contact hole and a second contact hole are formed in the dielectric layer, respectively on the gate structure and the source/drain region, and a third contact hole is formed in the dielectric layer, wherein the third contact hole overlaps the first contact hole and the second contact hole.
摘要翻译：在本发明中公开了一种半导体器件的制造方法。首先，在衬底上形成至少一个栅极结构和多个源极/漏极区域，然后在衬底上形成电介质层，在电介质层中分别在栅极上形成第一接触孔和第二接触孔结构和源极/漏极区，以及在电介质层中形成第三接触孔，其中第三接触孔与第一接触孔和第二接触孔重叠。

6. 发明授权

US08952392B2 Semiconductor structure and process thereof 有权
标题翻译：半导体结构及其工艺
公开(公告)号：US08952392B2
公开(公告)日：2015-02-10
申请号：US13369260
申请日：2012-02-08
申请人： Chieh-Te Chen , Yi-Po Lin , Jiunn-Hsiung Liao , Shui-Yen Lu , Li-Chiang Chen
发明人： Chieh-Te Chen , Yi-Po Lin , Jiunn-Hsiung Liao , Shui-Yen Lu , Li-Chiang Chen
IPC分类号： H01L29/15 , H01L21/336
CPC分类号： H01L28/20 , H01L21/76897 , H01L27/0629 , H01L28/24 , H01L29/66545
摘要： A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.
摘要翻译：半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。衬底具有隔离结构。抗蚀剂层位于隔离结构上。介电材料位于抗蚀剂层上。两个U形金属层位于电介质材料的两侧和抗蚀剂层上。两个金属分别位于两个U形金属层上。以这种方式提供了用于形成所述半导体结构的半导体工艺。

7. 发明申请

US20130200393A1 SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
标题翻译：半导体结构及其工艺
公开(公告)号：US20130200393A1
公开(公告)日：2013-08-08
申请号：US13369260
申请日：2012-02-08
申请人： Chieh-Te Chen , Yi-Po Lin , Jiunn-Hsiung Liao , Shui-Yen Lu , Li-Chiang Chen
发明人： Chieh-Te Chen , Yi-Po Lin , Jiunn-Hsiung Liao , Shui-Yen Lu , Li-Chiang Chen
IPC分类号： H01L29/16 , H01L21/28
CPC分类号： H01L28/20 , H01L21/76897 , H01L27/0629 , H01L28/24 , H01L29/66545
摘要： A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.
摘要翻译：半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。衬底具有隔离结构。抗蚀剂层位于隔离结构上。介电材料位于抗蚀剂层上。两个U形金属层位于电介质材料的两侧和抗蚀剂层上。两个金属分别位于两个U形金属层上。以这种方式提供了用于形成所述半导体结构的半导体工艺。

8. 发明授权

US08552503B2 Strained silicon structure 有权
标题翻译：应变硅结构
公开(公告)号：US08552503B2
公开(公告)日：2013-10-08
申请号：US12957304
申请日：2010-11-30
申请人： Guang-Yaw Hwang , Ling-Chun Chou , I-Chang Wang , Shin-Chuan Huang , Jiunn-Hsiung Liao , Shin-Chi Chen , Pau-Chung Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chieh-Te Chen
发明人： Guang-Yaw Hwang , Ling-Chun Chou , I-Chang Wang , Shin-Chuan Huang , Jiunn-Hsiung Liao , Shin-Chi Chen , Pau-Chung Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chieh-Te Chen
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/088 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.
摘要翻译：应变硅衬底结构包括设置在衬底上的第一晶体管和第二晶体管。第一晶体管包括第一栅极结构和设置在第一栅极结构的两侧的两个第一源极/漏极区域。第一源极/漏极到栅极间距在每个第一源极/漏极区域和第一栅极结构之间。第二晶体管包括第二栅极结构和设置在第二栅极结构的两侧的两个源极/漏极掺杂区域。第二源极/漏极到栅极间距在每个第二源极/漏极区域和第二栅极结构之间。第一源极/漏极到栅极距离小于第二源极/漏极到栅极距离。

9. 发明申请

US20120132996A1 STRAINED SILICON STRUCTURE 有权
标题翻译：应变硅结构
公开(公告)号：US20120132996A1
公开(公告)日：2012-05-31
申请号：US12957304
申请日：2010-11-30
申请人： Guang-Yaw Hwang , Ling-Chun Chou , I-Chang Wang , Shin-Chuan Huang , Jiunn-Hsiung Liao , Shin-Chi Chen , Pau-Chung Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chieh-Te Chen
发明人： Guang-Yaw Hwang , Ling-Chun Chou , I-Chang Wang , Shin-Chuan Huang , Jiunn-Hsiung Liao , Shin-Chi Chen , Pau-Chung Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chieh-Te Chen
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.
摘要翻译：应变硅衬底结构包括设置在衬底上的第一晶体管和第二晶体管。第一晶体管包括第一栅极结构和设置在第一栅极结构的两侧的两个第一源极/漏极区域。第一源极/漏极到栅极间距在每个第一源极/漏极区域和第一栅极结构之间。第二晶体管包括第二栅极结构和设置在第二栅极结构的两侧的两个源极/漏极掺杂区域。第二源极/漏极到栅极间距在每个第二源极/漏极区域和第二栅极结构之间。第一源极/漏极到栅极距离小于第二源极/漏极到栅极距离。

10. 发明授权

US08835324B2 Method for forming contact holes 有权
标题翻译：形成接触孔的方法
公开(公告)号：US08835324B2
公开(公告)日：2014-09-16
申请号：US13174875
申请日：2011-07-01
申请人： Chieh-Te Chen , Yi-Po Lin , Feng-Yih Chang , Chih-Wen Feng , Shang-Yuan Tsai
发明人： Chieh-Te Chen , Yi-Po Lin , Feng-Yih Chang , Chih-Wen Feng , Shang-Yuan Tsai
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/76816
摘要： In an exemplary method for forming contact holes, a substrate overlaid with an etching stop layer and an interlayer dielectric layer in that order is firstly provided. A first etching process then is performed to form at least a first contact opening in the interlayer dielectric layer. A first carbon-containing dielectric layer subsequently is formed overlying the interlayer dielectric layer and filling into the first contact opening. After that, a first anti-reflective layer and a first patterned photo resist layer are sequentially formed in that order overlying the carbon-containing dielectric layer. Next, a second etching process is performed by using the first patterned photo resist layer as an etching mask to form at least a second contact opening in the interlayer dielectric layer.
摘要翻译：在形成接触孔的示例性方法中，首先提供覆盖有蚀刻停止层和层间电介质层的基板。然后执行第一蚀刻工艺以在层间电介质层中形成至少第一接触开口。随后形成第一含碳介电层，覆盖层间电介质层并填充到第一接触开口中。之后，依次形成第一抗反射层和第一图案化光致抗蚀剂层，以覆盖含碳电介质层的顺序。接下来，通过使用第一图案化光致抗蚀剂层作为蚀刻掩模来进行第二蚀刻工艺，以在层间电介质层中形成至少第二接触开口。

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