专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090039448A1 THIN FILM TRANSISTOR, PIXEL STRUCTURE AND LIQUID CRYSTAL DISPLAY PANEL 有权
标题翻译：薄膜晶体管，像素结构和液晶显示面板
公开(公告)号：US20090039448A1
公开(公告)日：2009-02-12
申请号：US11924615
申请日：2007-10-26
申请人： Chiao-Shun Chuang , Fang-Chung Chen , Han-Ping David Shieh
发明人： Chiao-Shun Chuang , Fang-Chung Chen , Han-Ping David Shieh
IPC分类号： H01L31/02
CPC分类号： G02F1/133514 , G02F1/133345 , G02F1/133617 , G02F1/1368 , G02F2001/136222 , G02F2202/046 , G02F2202/36
摘要： A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low.
摘要翻译：设置在基板上的薄膜晶体管。薄膜晶体管包括栅极，半导电层，栅极绝缘体，源极和漏极。栅极绝缘体位于栅极和半导体层之间。光通过栅极绝缘体后显示特定的颜色。源极和漏极设置在半导体层上。还提供了具有像素结构的像素结构和液晶显示面板。液晶显示面板可以在不附加滤色器阵列的情况下显示彩色图像，使得液晶面板的制造过程简单，并且液晶面板的制造成本低。

2. 发明授权

US08907325B2 Thin film transistor having highly dielectric organic layer 有权
标题翻译：具有高介电有机层的薄膜晶体管
公开(公告)号：US08907325B2
公开(公告)日：2014-12-09
申请号：US11924615
申请日：2007-10-26
申请人： Chiao-Shun Chuang , Fang-Chung Chen , Han-Ping David Shieh
发明人： Chiao-Shun Chuang , Fang-Chung Chen , Han-Ping David Shieh
IPC分类号： H01L29/08 , H01L35/24 , H01L29/10 , G02F1/1335 , G02F1/1333 , G02F1/1368 , G02F1/1362
CPC分类号： G02F1/133514 , G02F1/133345 , G02F1/133617 , G02F1/1368 , G02F2001/136222 , G02F2202/046 , G02F2202/36
摘要： A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low.
摘要翻译：设置在基板上的薄膜晶体管。薄膜晶体管包括栅极，半导电层，栅极绝缘体，源极和漏极。栅极绝缘体位于栅极和半导体层之间。光通过栅极绝缘体后显示特定的颜色。源极和漏极设置在半导体层上。还提供了具有像素结构的像素结构和液晶显示面板。液晶显示面板可以在不附加滤色器阵列的情况下显示彩色图像，使得液晶面板的制造过程简单，并且液晶面板的制造成本低。

3. 发明申请

US20070102697A1 JUNCTION STRUCTURE OF ORGANIC SEMICONDUCTOR DEVICE, ORGANIC THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：有机半导体器件的结构结构，有机薄膜晶体管及其制造方法
公开(公告)号：US20070102697A1
公开(公告)日：2007-05-10
申请号：US11164092
申请日：2005-11-10
申请人： Fang-Chung Chen , Chiao-Shun Chuang
发明人： Fang-Chung Chen , Chiao-Shun Chuang
IPC分类号： H01L29/08
CPC分类号： H01L51/105 , H01L51/057
摘要： A junction structure of an organic semiconductor device including an organic semiconductor layer, a conductive layer and a modifying layer is provided. The modifying layer is formed between the organic semiconductor layer and the conductive layer, wherein the modifying layer includes an inorganic compound or an organic complex compound. An organic thin film transistor including a gate, a source/drain, a dielectric layer, an organic semiconductor layer and at least a modifying layer is also provided. The gate is electrically isolated from the source/drain. The dielectric layer is disposed between the gate and the source/drain. The organic semiconductor layer is disposed between the source and the drain. The modifying layer is disposed between the organic semiconductor layer and the source/drain, wherein the modifying layer includes an inorganic compound or an organic complex compound.
摘要翻译：提供了包括有机半导体层，导电层和改性层的有机半导体器件的结结构。在有机半导体层和导电层之间形成改性层，其中改性层包括无机化合物或有机络合物。还提供了包括栅极，源极/漏极，电介质层，有机半导体层和至少改性层的有机薄膜晶体管。栅极与源极/漏极电隔离。电介质层设置在栅极和源极/漏极之间。有机半导体层设置在源极和漏极之间。改性层设置在有机半导体层和源极/漏极之间，其中改性层包括无机化合物或有机络合物。

4. 发明申请

US20070158647A1 JUNCTION STRUCTURE OF ORGANIC SEMICONDUCTOR DEVICE, ORGANIC THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF 审中-公开
公开(公告)号：US20070158647A1
公开(公告)日：2007-07-12
申请号：US11467165
申请日：2006-08-25
申请人： Fang-Chung Chen , Chiao-Shun Chuang , Dong-Sian Chen , Li-Jen Kung , Yung-Sheng Lin , Chuan-Yi Wu
发明人： Fang-Chung Chen , Chiao-Shun Chuang , Dong-Sian Chen , Li-Jen Kung , Yung-Sheng Lin , Chuan-Yi Wu
IPC分类号： H01L29/08 , H01L35/24 , H01L51/00
CPC分类号： H01L51/105 , H01L51/057
摘要： A junction structure of an organic semiconductor device including an organic semiconductor layer, a conductive layer and a modifying layer is provided. The modifying layer is formed between the organic semiconductor layer and the conductive layer, wherein the modifying layer includes an inorganic compound or an organic complex compound. An organic thin film transistor including a gate, a source/drain, a dielectric layer, an organic semiconductor layer and at least a modifying layer is also provided. The gate is electrically isolated from the source/drain. The dielectric layer is disposed between the gate and the source/drain. The organic semiconductor layer is disposed between the source and the drain. The modifying layer is disposed between the organic semiconductor layer and the source/drain, wherein the modifying layer includes an inorganic compound or an organic complex compound.

5. 发明申请

US20070215957A1 GATE DIELECTRIC STRUCTURE AND AN ORGANIC THIN FILM TRANSISTOR BASED THEREON 审中-公开
标题翻译：盖特电介质结构及其有机薄膜晶体管
公开(公告)号：US20070215957A1
公开(公告)日：2007-09-20
申请号：US11459409
申请日：2006-07-24
申请人： Fang-Chung Chen , Chiao-Shun Chuang , Yung-Sheng Lin
发明人： Fang-Chung Chen , Chiao-Shun Chuang , Yung-Sheng Lin
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L51/0537 , H01L51/0529
摘要： A gate dielectric structure and an organic thin film transistor based thereon, wherein the gate dielectric structure comprises: an organic-inorganic composite layer and an organic insulation layer, and the gate dielectric structure is applied to an organic thin film transistor. As the organic-inorganic composite layer of the gate dielectric structure has an organic insulation matrix blended with inorganic surface-modified particles, it can achieve a high dielectric constant. Further, as the organic insulation layer can modify the surface of the organic-inorganic composite layer, not only the leakage current is reduced, but also the crystalline structure of the organic semiconductor layer becomes more orderly. Thus, the carrier mobility is raised, the current output of the element is increased, and the performance of the element is also greatly enhanced.
摘要翻译：一种栅极电介质结构和基于其的有机薄膜晶体管，其中所述栅极介电结构包括：有机 - 无机复合层和有机绝缘层，并且所述栅极电介质结构被施加到有机薄膜晶体管。由于栅极电介质结构的有机 - 无机复合层具有与无机表面改性粒子混合的有机绝缘基体，因此可以实现高介电常数。此外，由于有机绝缘层可以改变有机 - 无机复合层的表面，不仅漏电流降低，而且有机半导体层的晶体结构变得更有序。因此，载流子迁移率提高，元件的电流输出增加，元件的性能也大大提高。

6. 发明授权

US07087958B2 Termination structure of DMOS device 有权
标题翻译： DMOS设备终端结构
公开(公告)号：US07087958B2
公开(公告)日：2006-08-08
申请号：US10771957
申请日：2004-02-03
申请人： Chiao-Shun Chuang , Chien-Ping Chang , Mao-Song Tseng , Hsing-Huang Hsieh
发明人： Chiao-Shun Chuang , Chien-Ping Chang , Mao-Song Tseng , Hsing-Huang Hsieh
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L29/402 , H01L29/407 , H01L29/7813
摘要： In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and includes an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features. The trench-typed MOSFET and the trench-typed termination structure may be formed on a DMOS device including an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure may penetrate through the P epitaxial layer into the N epitaxial layer.
摘要翻译：在本发明的一个实施例中，半导体器件组包括至少一个沟槽型MOSFET和沟槽型端接结构。沟槽型MOSFET具有沟槽轮廓并且在沟槽轮廓中包括栅极氧化物层，并且在栅极氧化物层上包括多晶硅层。沟槽式端接结构具有沟槽轮廓并且在沟槽轮廓中包括氧化物层。具有离散特征的端接多晶硅层分离端接多晶硅层。隔离层覆盖终端多晶硅层并填充离散特征。沟槽型MOSFET和沟槽型端接结构可以形成在包括N +硅衬底，N +硅衬底上的N外延层和N外延层上的P外延层的DMOS器件上。沟槽型MOSFET和沟槽型端接结构的沟槽轮廓可以穿透P外延层进入N外延层。

7. 发明授权

US06677223B2 Transistor with highly uniform threshold voltage 有权
标题翻译：具有高度均匀阈值电压的晶体管
公开(公告)号：US06677223B2
公开(公告)日：2004-01-13
申请号：US10219092
申请日：2002-08-13
申请人： Chiao-Shun Chuang , Chien-Ping Chang , Mao-Song Tseng , Hsin-Huang Hsieh
发明人： Chiao-Shun Chuang , Chien-Ping Chang , Mao-Song Tseng , Hsin-Huang Hsieh
IPC分类号： H01L2120
CPC分类号： H01L21/28167
摘要： Embodiments of the present invention relate to processes utilized in the manufacturing of a semiconductor device having transistors to achieve high uniformity of threshold voltages. The invention does so by ensuring high uniformity of impurity concentration in the substrate. In one embodiment, a method for manufacturing a semiconductor device having transistors with high uniformity of threshold voltages comprises providing a substrate and a source of impurities, and disposing the substrate and the source of impurities in a first oxygen gas at a first initial temperature and heated to a first target temperature at a first temperature rate to drive the impurities into the substrate. The first initial temperature is sufficiently low to prevent the oxygen from diffusing into the substrate. The substrate is disposed in a second oxygen gas at a second initial temperature and heated to a second target temperature at a second rate to form an oxide layer on the substrate. The second rate is high enough for rapid formation of the oxide layer on the substrate so as to prevent the impurities driven into the substrate from diffusing out from the substrate.
摘要翻译：本发明的实施例涉及用于制造具有晶体管以实现阈值电压的高均匀性的半导体器件的工艺。本发明通过确保衬底中杂质浓度的高均匀性来实现。在一个实施例中，制造具有高阈值电压均匀性的晶体管的半导体器件的方法包括提供衬底和杂质源，并将衬底和杂质源置于第一初始温度的第一氧气中并加热以第一温度速率升至第一目标温度以驱动杂质进入基板。第一初始温度足够低以防止氧扩散到基底中。将衬底在第二初始温度下设置在第二氧气中，并以第二速率加热至第二目标温度，以在衬底上形成氧化物层。第二速率足够高以快速形成衬底上的氧化物层，以防止驱动到衬底中的杂质从衬底扩散出来。

8. 发明授权

US08912621B1 Trench schottky devices 有权
标题翻译：沟槽肖特基器件
公开(公告)号：US08912621B1
公开(公告)日：2014-12-16
申请号：US13546867
申请日：2012-07-11
申请人： Chiao-Shun Chuang , Kai-Yu Chen , Cheng-Chin Huang
发明人： Chiao-Shun Chuang , Kai-Yu Chen , Cheng-Chin Huang
IPC分类号： H01L29/47
CPC分类号： H01L29/872 , H01L29/66143
摘要： During fabrication of a semiconductor device, a width of semiconductor mesas between isolation trenches in the semiconductor device is varied in different regions. In particular, the width of the mesas is smaller in a termination region of the semiconductor device than in a cell or active region. When an oxide layer is subsequently grown, the semiconductor mesas between the trenches in the termination region are at least partially consumed so that the semiconductor mesas in the cell region and the termination region have different heights. Therefore, a contact photomask is not needed to isolate the semiconductor mesas in the termination region. Furthermore, after a planarization operation (such as chemical mechanical polishing), the semiconductor device may have a planar top surface than if contact holes are created. This may allow the metal layer deposited on top of the cell region and the termination region to be flat.
摘要翻译：在制造半导体器件期间，半导体器件中的隔离沟槽之间的半导体台面的宽度在不同的区域中变化。特别地，在半导体器件的端接区域中，台面的宽度小于单元或有源区域中的宽度。当随后生长氧化物层时，终止区域中的沟槽之间的半导体台面至少部分消耗，使得单元区域和端接区域中的半导体台面具有不同的高度。因此，不需要接触光掩模来隔离终端区域中的半导体台面。此外，在平面化操作（例如化学机械抛光）之后，半导体器件可以具有比产生接触孔的平坦的顶表面。这可以使沉积在电池区域和终端区域顶部的金属层变平坦。

9. 发明授权

US08314471B2 Trench devices having improved breakdown voltages and method for manufacturing same 有权
标题翻译：具有改进的击穿电压的沟槽装置及其制造方法
公开(公告)号：US08314471B2
公开(公告)日：2012-11-20
申请号：US12620473
申请日：2009-11-17
申请人： Chiao-Shun Chuang , Tony Huang
发明人： Chiao-Shun Chuang , Tony Huang
IPC分类号： H01L29/02
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to disperse an electric field.
摘要翻译：在一个实施例中，本发明包括半导体功率器件。半导体功率器件包括沟槽栅极和沟槽场区域。沟槽栅极垂直设置在半导体衬底的沟槽内。沟槽场区域垂直设置在沟槽内并且在沟槽栅极下方。沟槽场区域的下部逐渐变细以分散电场。

10. 发明授权

US07084457B2 DMOS device having a trenched bus structure 有权
标题翻译：具有沟槽总线结构的DMOS器件
公开(公告)号：US07084457B2
公开(公告)日：2006-08-01
申请号：US10774212
申请日：2004-02-05
申请人： Hsin-Huang Hsieh , Chiao-Shun Chuang , Chien-Ping Chang , Mao-Song Tseng
发明人： Hsin-Huang Hsieh , Chiao-Shun Chuang , Chien-Ping Chang , Mao-Song Tseng
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/7811 , H01L29/4232 , H01L29/4238 , H01L29/7813
摘要： A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.
摘要翻译：引入了具有沟槽总线结构的DMOS器件。沟槽总线结构包括形成在P基板上的场氧化物层和从场氧化物层的顶表面向下延伸到P衬底的下部的沟槽。形成栅极氧化层和多晶硅母线，以填充沟槽作为总线结构的主要部分。此外，在多晶硅总线和场氧化物层的顶部形成隔离层和金属线。在隔离层中形成开口以形成多晶硅母线和金属线之间的连接。在具体实施例中，同时形成DMOS器件的总线沟槽和栅极沟槽，同时形成多晶硅母线和栅电极。因此，总线结构能够形成DMOS晶体管，而不需要用于定义多晶硅总线位置的任何光刻步骤。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式