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1. 发明授权

US06201269B1 Junction field effect transistor and method of producing the same 失效
标题翻译：结场效应晶体管及其制造方法
公开(公告)号：US06201269B1
公开(公告)日：2001-03-13
申请号：US08458724
申请日：1995-06-02
申请人： Chiaki Takano , Hidetoshi Kawasaki , Masaru Wada
发明人： Chiaki Takano , Hidetoshi Kawasaki , Masaru Wada
IPC分类号： H01L2976
CPC分类号： H01L29/66924 , H01L21/8252 , H01L27/0605 , H01L27/0629 , H01L29/0649 , H01L29/1066 , H01L29/808
摘要： For suppressing generation of leakage current and side-gate effect in a junction field effect transistor, a gate extension is formed on a semi-insulative compound semiconductor substrate in a manner to extend from a gate and to protrude outward beyond a channel transversely thereto, and an insulating layer is formed on the semi-insulative compound semiconductor substrate under the gate extension. A method of producing this transistor comprises the steps of first forming a channel and a source-drain on a substrate, then forming a gate on the channel together with a gate extension which extends from the gate and protrudes outward beyond the channel transversely thereto, and forming an insulating layer adjacently to the channel and the source-drain in such a manner that no gap is existent between the insulating layer and at least the channel.
摘要翻译：为了抑制结型场效应晶体管中的漏电流和侧栅效应的产生，在半绝缘化合物半导体基板上以从栅极延伸并向外突出超过横向通道的方式形成栅极延伸，以及在栅极延伸部分的半绝缘性化合物半导体基板上形成绝缘层。制造该晶体管的方法包括以下步骤：首先在衬底上形成沟道和源极 - 漏极，然后在沟道上形成栅极以及从栅极延伸并从其横向向外突出超过沟槽的栅极延伸，以及以与绝缘层和至少沟道之间不存在间隙的方式形成与沟道和源极 - 漏极相邻的绝缘层。

2. 发明授权

US07616043B2 Methods and apparatus for managing LSI power consumption and degradation using clock signal conditioning 有权
标题翻译：使用时钟信号调理来管理LSI功耗和劣化的方法和装置
公开(公告)号：US07616043B2
公开(公告)日：2009-11-10
申请号：US12029764
申请日：2008-02-12
申请人： Chiaki Takano
发明人： Chiaki Takano
IPC分类号： H03K3/00
CPC分类号： H03K19/0016
摘要： Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where a sum of the first and second on-times is approximately equal to a sum of off-times each period; distributing the first clock signal through a distribution tree and terminating at a plurality of final buffer circuits that produce respective distributed clock signals from which respective second clock signals are produced to supply at least a portion of the integrated circuit; deleting the second on-pulse from each of the distributed clock signals each period to produce the respective second clock signals, the second clock signals each including at least a portion of the first on-pulse, but none of the second on-pulse each period.
摘要翻译：用于将时钟信号分配到集成电路的方法和装置提供：在慢速操作模式下产生具有分别具有不同的第一和第二接通时间的每个周期的至少第一和第二导通脉冲的第一时钟信号，其中，第一和第二接通时间的总和近似等于每个周期的关闭时间的总和; 通过分配树分配第一时钟信号并终止于产生各自的分布式时钟信号的多个最终缓冲器电路，从其产生相应的第二时钟信号以提供集成电路的至少一部分; 从每个周期的每个分布式时钟信号中删除第二导通脉冲以产生相应的第二时钟信号，所述第二时钟信号各自包括第一接通脉冲的至少一部分，但是每个周期中没有第二导通脉冲。

3. 发明授权

US5329254A Semiconductor integrated circuit having clock signal generator 失效
标题翻译：具有时钟信号发生器的半导体集成电路
公开(公告)号：US5329254A
公开(公告)日：1994-07-12
申请号：US924515
申请日：1992-08-04
申请人： Chiaki Takano
发明人： Chiaki Takano
IPC分类号： H03L7/06 , G06F1/06 , G06F1/08 , G11C11/407 , H03K3/03 , H03L7/089 , H03L7/099 , H03L7/183 , H03B5/00
CPC分类号： H03L7/0997 , G06F1/08 , H03K3/0315 , H03L7/089 , H03L7/183
摘要： A semiconductor integrated circuit having a clock signal generator comprising a ring oscillator, a divider, a phase comparator, and an up-down counter. The ring oscillator provides variable oscillation frequencies determined by a sum of the delay times provided by the circuit elements constituting the oscillator. The divider divides the oscillation frequency from the ring oscillator by a specified number. The phase comparator compares the frequency of the signal from the divider with the frequency of the external clock signal. The up-down counter controls the oscillation frequency of the ring oscillator by selectively operating switches connected with the ring oscillator based on the comparison result from the comparator. The clock generator is controlled by an external clock signal to generate an internal clock signal having a higher frequency and outputs both signals. This makes it possible to constitute the semiconductor integrated circuit by using the digital integrated circuit technology alone, thereby allowing the slow operating semiconductors and fast operating semiconductors to exist on the same circuit without sacrificing the excellent characteristics of the latter.
摘要翻译：一种具有时钟信号发生器的半导体集成电路，包括环形振荡器，分频器，相位比较器和升降计数器。环形振荡器提供由构成振荡器的电路元件提供的延迟时间之和确定的可变振荡频率。分频器将振荡频率与环形振荡器分开一定数量。相位比较器将来自分频器的信号的频率与外部时钟信号的频率进行比较。上位计数器根据比较器的比较结果选择性地连接环形振荡器的开关来控制环形振荡器的振荡频率。时钟发生器由外部时钟信号控制，以产生具有较高频率的内部时钟信号并输出两个信号。这使得可以通过单独使用数字集成电路技术来构成半导体集成电路，从而允许在同一电路上缓慢运行半导体和快速操作半导体，而不牺牲后者的优异特性。

4. 发明授权

US07733150B2 Method and apparatus for adaptive clock phase control for LSI power reduction 有权
标题翻译：用于LSI功率降低的自适应时钟相位控制的方法和装置
公开(公告)号：US07733150B2
公开(公告)日：2010-06-08
申请号：US12192385
申请日：2008-08-15
申请人： Chiaki Takano
发明人： Chiaki Takano
IPC分类号： G06F1/04
CPC分类号： H03K5/13 , H03K5/1506 , H03K2005/00039 , H03K2005/0013
摘要： Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.
摘要翻译：用于将时钟信号分配给数字电路的方法和装置提供：产生时钟信号; 并且延迟，提前或者使时钟信号不变以产生作为控制信号的函数的输出时钟信号，其中时钟信号和输出时钟信号之间的延迟或提前量（相位差）是时间的函数变化到数字电路的电源电压的大小。

5. 发明授权

US07301385B2 Methods and apparatus for managing clock skew 有权
标题翻译：管理时钟偏移的方法和装置
公开(公告)号：US07301385B2
公开(公告)日：2007-11-27
申请号：US11233423
申请日：2005-09-22
申请人： Chiaki Takano , Stephen D. Weitzel
发明人： Chiaki Takano , Stephen D. Weitzel
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having a second frequency, synchronize the second signal with the first signal, and propagate the synchronized second signal to at least one other clock mesh of the apparatus.
摘要翻译：公开了一种装置，其包括提供具有第一频率的第一信号的信号发生器; 时钟树，用于将所述第一信号传播到所述装置的至少一个时钟网格; 以及最终缓冲器，用于接收第一信号，提供具有第二频率的第二信号，使第二信号与第一信号同步，并将同步的第二信号传播到装置的至少一个其它时钟网格。

6. 发明授权

US5357122A Three-dimensional optical-electronic integrated circuit device with raised sections 失效
标题翻译：具有凸起部分的三维光电集成电路器件
公开(公告)号：US5357122A
公开(公告)日：1994-10-18
申请号：US939694
申请日：1992-09-02
申请人： Akihiko Okubora , Chiaki Takano , Kiyoshi Tanaka , Hideto Ishikawa
发明人： Akihiko Okubora , Chiaki Takano , Kiyoshi Tanaka , Hideto Ishikawa
IPC分类号： G02B6/42 , G02B6/43 , H01L23/48 , H01L25/065 , H01L27/144 , H01L27/15 , H01L27/14
CPC分类号： G02B6/43 , H01L23/48 , H01L25/0657 , H01L27/1443 , H01L27/15 , G02B6/4214 , H01L2225/06534 , H01L2225/06565 , H01L2924/0002
摘要： An optical-electronic integrated circuit device capable of three-dimensionally transmitting optical signals between plural semiconductor substrates on each of which an integrated circuit is previously formed. At least one of the light emitting elements and the light receiving elements are formed on the semiconductor substrate which transmits the light propagated between these elements. In this manner, signals may be transmitted in a direction perpendicular to the semiconductor substrate even without specifically processing the semiconductor substrate. Additionally, signal distortion, transmission losses, mutual intervention or delay are not incurred. For two-dimensionally connecting plural three-dimensionally integrated optical-electronic integrated circuit devices in a direction parallel to the semiconductor substrates, the circuit devices are arrayed on an optical interconnection base plate, and light signals are transmitted by means of a pair of inclined surfaces which are formed on the optical interconnection base plate and which are arranged facing the light emitting element and the light receiving element, and the light waveguide channels defined between these inclined surfaces. This drastically increases the operating speed of the circuit device and the integration degree.
摘要翻译：一种能够在预先形成有集成电路的多个半导体基板之间三维地发送光信号的光电集成电路装置。发光元件和光接收元件中的至少一个形成在半导体衬底上，透射在这些元件之间传播的光。以这种方式，即使没有具体地处理半导体衬底，也可以在垂直于半导体衬底的方向上传输信号。此外，不会发生信号失真，传输损耗，相互干预或延迟。为了在与半导体基板平行的方向上二维地连接多个三维集成的光电集成电路器件，电路器件被排列在光互连基板上，并且光信号通过一对倾斜表面它们形成在光学互连基板上并且被布置成面向发光元件和光接收元件以及限定在这些倾斜表面之间的光波导通道。这大大提高了电路设备的工作速度和集成度。

7. 发明授权

US07676683B2 Method and system for rebooting a processor in a multi-processor system 失效
标题翻译：在多处理器系统中重新启动处理器的方法和系统
公开(公告)号：US07676683B2
公开(公告)日：2010-03-09
申请号：US11509493
申请日：2006-08-24
申请人： Atsushi Tsuji , Chiaki Takano , Atsuo Mangyo , Masaaki Nozaki , Shunsaku Tokito , Hiroaki Terakawa
发明人： Atsushi Tsuji , Chiaki Takano , Atsuo Mangyo , Masaaki Nozaki , Shunsaku Tokito , Hiroaki Terakawa
IPC分类号： G06F1/00 , G06F9/00 , G06F13/00 , G06F12/00
CPC分类号： G06F9/4418
摘要： Processors arranged in a multi-processor configuration for substantially parallel operations receive their initialization data in order to start operations, such as graphics computations, real-time multimedia streaming, etc. Due to a change in the processing load, one or more processors might be deactivated. Subsequently, the load increases to such a level that requires all or some of the deactivated processors to be active again. In this case, the boot-up process of the entire system is not carried out as it would be time-consuming and wasteful; instead, responsive to a control signal only those processors that were previously in inactive mode are re-initialized by selecting a configuration data supplied by another processor, controller or any other intelligent programmable device. Alternatively, the configuration data may be accessed and retrieved from a local storage medium individually located in each processor, thereby re-booting only those inactive processors and without re-initializing the entire system.
摘要翻译：以多处理器配置布置的用于基本并行操作的处理器接收它们的初始化数据，以便开始诸如图形计算，实时多媒体流等操作。由于处理负载的变化，一个或多个处理器可能是停用随后，负载增加到要求全部或一些停用处理器再次活动的水平。在这种情况下，整个系统的启动过程不会执行，因为这将是耗时且浪费的; 相反，响应于控制信号，仅通过选择由另一个处理器，控制器或任何其他智能可编程设备提供的配置数据来重新初始化先前处于非活动模式的处理器。或者，可以从单独位于每个处理器中的本地存储介质访问和检索配置数据，从而仅重新引导那些不活动的处理器，并且不重新初始化整个系统。

8. 发明授权

US07233188B1 Methods and apparatus for reducing power consumption in a processor using clock signal control 有权
标题翻译：使用时钟信号控制来降低处理器功耗的方法和装置
公开(公告)号：US07233188B1
公开(公告)日：2007-06-19
申请号：US11318228
申请日：2005-12-22
申请人： Chiaki Takano , Daniel Lawrence Stasiak , Nathan Paul Chelstrom , Steven Ross Ferguson
发明人： Chiaki Takano , Daniel Lawrence Stasiak , Nathan Paul Chelstrom , Steven Ross Ferguson
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/126 , Y02D10/128
摘要： Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.
摘要翻译：方法和装置提供：产生指示睡眠模式的第一基本上稳定的状态逻辑电平的控制信号，以及指示正常模式的第二基本稳定的逻辑电平; 当控制信号处于第一逻辑电平时产生处于基本稳态零电平的门信号，并且当控制信号处于第二逻辑电平时以当地时钟频率振荡; 根据门信号从系统时钟信号产生本地时钟信号; 并且在控制信号的原点与产生栅极信号的位置之间插入至少一个信号传播锁存电路。

9. 发明申请

US20070011531A1 Methods and apparatus for managing clock skew between clock domain boundaries 有权
标题翻译：用于管理时钟域边界之间的时钟偏移的方法和装置
公开(公告)号：US20070011531A1
公开(公告)日：2007-01-11
申请号：US11149103
申请日：2005-06-09
申请人： Chiaki Takano
发明人： Chiaki Takano
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/31726
摘要： Methods and apparatus provide for: a plurality of stages of combinational logic, each stage including a full latch circuit operable to transfer data into the given stage of combinational logic and a transparent latch circuit operable transfer output data from the given stage of combinational logic to a next of the stages; in each stage, passing state changes of output data from the given combinational logic irrespective of when such changes occur when a clock signal of the transparent latch circuit is at a first of two logic levels; and in each stage, withholding state changes of the output data until the clock signal of the transparent latch circuit transitions from the second of the two logic levels to the first logic level.
摘要翻译：方法和装置提供：多级的组合逻辑，每级包括可操作以将数据传送到组合逻辑的给定级的完全锁存电路和透明锁存电路，可操作地将组合逻辑的给定阶段的输出数据传送到接下来的阶段; 无论在透明锁存电路的时钟信号是否处于两个逻辑电平中的第一个时，何时发生这种变化，在每个阶段都将来自给定组合逻辑的输出数据的状态变化通过; 并且在每个阶段中，直到透明锁存电路的时钟信号从两个逻辑电平中的第二逻辑电平转换到第一逻辑电平为止，输出数据保持状态变化。

10. 发明申请

US20080133989A1 Method And Apparatus For Scan Chain Circuit AC Test 审中-公开
标题翻译：扫描链电路交流测试方法与装置
公开(公告)号：US20080133989A1
公开(公告)日：2008-06-05
申请号：US11566819
申请日：2006-12-05
申请人： Atsushi Hayashi , Chiaki Takano , Noriyuki Oshima , Takeshi Inoue , Hiroki Kihara , Yoichi Nishino
发明人： Atsushi Hayashi , Chiaki Takano , Noriyuki Oshima , Takeshi Inoue , Hiroki Kihara , Yoichi Nishino
IPC分类号： G01R31/3185
CPC分类号： G01R31/318536 , G01R31/318541 , G01R31/318555
摘要： Methods and apparatus for dynamically (AC) testing a target circuit within a main circuit include: providing respective sets of input latches from among a plurality of latches of the main circuit; reconfiguring connections of at least some of the input latches from normal connections within the main circuit such that each set of input latches is connected in series and directs an input bit stream from an associated source node into an associated input node of the target circuit; scanning a plurality of sets of input bits into the respective sets of input latches such that each latch of each set of input latches contains a respective bit of an associated one of the sets of input bits; and scanning each of the sets of input bits serially into the respective input nodes of the target circuit at a sufficiently high frequency to dynamically test the target circuit.
摘要翻译：用于动态（AC）测试主电路内的目标电路的方法和装置包括：从主电路的多个锁存器中提供各组输入锁存器; 重新配置至少一些输入锁存器与主电路内的正常连接的连接，使得每组输入锁存器串联连接，并将输入比特流从相关源节点引导到目标电路的相关输入节点; 将多组输入位扫描到相应的输入锁存器组中，使得每组输入锁存器的每个锁存器包含输入位组中相关联的一个组的相应位; 并且以足够高的频率将每组输入位串行地扫描到目标电路的相应输入节点中以动态测试目标电路。

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