专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06269430B1 Method for controlling a process of writing data sent by a central processing unit to a memory by using a central processing unit interface 有权
标题翻译：用于通过使用中央处理单元接口来控制将由中央处理单元发送的数据写入存储器的处理的方法
公开(公告)号：US06269430B1
公开(公告)日：2001-07-31
申请号：US09342711
申请日：1999-06-29
申请人： Chia-Hsin Chen , You-Ming Chiu , Jiin Lai
发明人： Chia-Hsin Chen , You-Ming Chiu , Jiin Lai
IPC分类号： G06F1200
CPC分类号： G06F12/0875 , G06F13/4243 , G06F2212/303
摘要： A method for a CPU interface to control a writing process that writes data sent from a CPU to a memory. The CPU interface controls the writing process through steps mainly including receiving a write request and data from a CPU, sending a dummy request to the memory control circuit of the memory circuit, and then writing the data to a memory of the memory circuit. After the CPU interface receives a write request from the CPU, the CPU interface sends a dummy request to the memory control circuit to pre-charge and activate the designative memory page of the memory circuit before the data is sent to the memory circuit. Since the designative memory page is always pre-charged and activated while the data is received at the memory control circuit, the memory control circuit sends only a write command to the memory for writing the data to the memory without further pre-charging and activating the designative memory page. Therefore, the total number of clock cycles required for processing a write request is shortened.
摘要翻译：一种CPU接口的方法，用于控制将从CPU发送到存储器的数据写入的写入过程。 CPU接口通过主要包括从CPU接收写入请求和数据，向存储器电路的存储器控制电路发送伪请求，然后将数据写入存储器电路的存储器的步骤来控制写入过程。在CPU接口从CPU接收到写请求之后，CPU接口向存储器控制电路发送伪请求，以在数据被发送到存储器电路之前对存储器电路的指定存储器页进行预充电和激活。由于在存储器控制电路中接收到数据时，指定存储器页面总是被预先充电并被激活，所以存储器控制电路仅将写入命令发送到存储器，用于将数据写入存储器，而无需进一步的预充电和激活指定记忆页面。因此，缩短了处理写请求所需的总时钟周期数。

2. 发明授权

US06687320B1 Phase lock loop (PLL) clock generator with programmable skew and frequency 有权
标题翻译：具有可编程偏移和频率的锁相环（PLL）时钟发生器
公开(公告)号：US06687320B1
公开(公告)日：2004-02-03
申请号：US09322072
申请日：1999-05-27
申请人： You-Ming Chiu , Jiin Lai , Jyhfong Lin , Hsin-Chieh Lin , Wei-Yu Wang
发明人： You-Ming Chiu , Jiin Lai , Jyhfong Lin , Hsin-Chieh Lin , Wei-Yu Wang
IPC分类号： H03D324
CPC分类号： H03L7/081 , G06F1/08 , G06F1/10 , H03L7/18
摘要： A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.
摘要翻译：在本发明中提供了具有可编程频率和偏斜的锁相环（PLL）时钟发生器，其中产生的时钟信号的频率可以被动态地改变，并且可以通过计算机程序动态地调整产生的时钟信号的偏移。此外，可以补偿由于负载变化引起的信号偏移。因此，基于闭环配置的PLL时钟发生器可以更好地控制时钟信号的偏斜，为系统提供更高的稳定性和耐久性。

3. 发明授权

US6020774A Gated clock tree synthesis method for the logic design 失效
标题翻译：门控时钟树的逻辑设计合成方法
公开(公告)号：US6020774A
公开(公告)日：2000-02-01
申请号：US121296
申请日：1998-07-23
申请人： You-Ming Chiu , Jiin Lai
发明人： You-Ming Chiu , Jiin Lai
IPC分类号： G06F1/10 , G06F17/50 , H03K1/04
CPC分类号： G06F17/505 , G06F1/10 , G06F2217/62
摘要： A gated clock tree synthesis (CTS) method is provided for the purpose of synthesizing a gate array logic circuit to allow optimal topological arrangement of the gate array on the logic circuit. This in turn allows the logic circuit to operate more efficiently. The logic circuit includes at least one clock generator, a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator, a plurality of first logic elements that are directly driven by the output clock signal from the clock generator, and a plurality of second logic elements that are driven by the gated clock signal outputted from each of the control gates under control by the control signal. The gated CTS method comprises the steps of grouping the first logic elements into a plurality of groups, connecting each group of the first logic elements via a first buffer to one of the control gates, connecting each of the second logic elements via a second buffer to the clock generator, and connecting one input end of each of the control gates to the clock generator.
摘要翻译：提供门控时钟树合成（CTS）方法用于合成门阵列逻辑电路以允许逻辑电路上的门阵列的最佳拓扑排列。这又允许逻辑电路更有效地操作。逻辑电路包括至少一个时钟发生器，多个控制栅极，每个控制栅极具有一个连接到控制信号的输入端，另一个输入端连接以从时钟发生器接收输出时钟信号;多个第一逻辑元件，由来自时钟发生器的输出时钟信号直接驱动，以及多个第二逻辑元件，其由控制信号控制的每个控制门输出的门控时钟信号驱动。门控CTS方法包括以下步骤：将第一逻辑元件分组成多个组，将每组第一逻辑元件经由第一缓冲器连接到控制门之一，将第二逻辑元件经由第二缓冲器连接到时钟发生器，并且将每个控制门的一个输入端连接到时钟发生器。

4. 发明授权

US06278641B1 Method and apparatus capable of programmably delaying clock of DRAM 有权
标题翻译：能够可编程地延迟DRAM的时钟的方法和装置
公开(公告)号：US06278641B1
公开(公告)日：2001-08-21
申请号：US09578234
申请日：2000-05-24
申请人： Chia-Hsin Chen , Jiin Lai
发明人： Chia-Hsin Chen , Jiin Lai
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , G11C11/4076
摘要： An apparatus and method capable of programmably delaying a clock of a memory. The apparatus and method utilize the BIOS, external electric switches or other logic devices to selectively delay the clock of the DRAM and/or the internal clock of the north bridge, by which the DRAM has enough setup time at the rising edge of work clock to correctly read out the command word. The north bridge can then correctly receive data from the DRAM module and transfer the data to the CPU or AGP. Therefore, the memory can function normally even if the memory is operated at high speed or with heavy loading.
摘要翻译：一种能够可编程地延迟存储器的时钟的装置和方法。该装置和方法利用BIOS，外部电气开关或其他逻辑装置来选择性地延迟DRAM的时钟和/或北桥的内部时钟，由此DRAM在工作时钟的上升沿具有足够的建立时间正确读出命令字。然后，北桥可以从DRAM模块正确接收数据，并将数据传输到CPU或AGP。因此，即使存储器以高速或大负载运行，存储器也能正常工作。

5. 发明授权

US06738880B2 Buffer for varying data access speed and system applying the same 有权
标题翻译：用于变化数据访问速度的缓冲器和应用它的系统
公开(公告)号：US06738880B2
公开(公告)日：2004-05-18
申请号：US09878896
申请日：2001-06-11
申请人： Jiin Lai , Chia-Hsin Chen , Nai-Shung Chang
发明人： Jiin Lai , Chia-Hsin Chen , Nai-Shung Chang
IPC分类号： G06F1300
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be enhanced. The buffer is coupled with a control chip set and several memory modules to provide functions of data analysis and assembly to satisfy a two-way data transmission interface and to obtain a higher data transmission rate. The buffer also has the function of isolating the electric connection between two sides. A single signal interface from a memory module can be converted to a complementary source synchronous signal by the buffer, so that a high-speed data transmission can be achieved. A memory system can apply several of such buffers to achieve an even higher data transmission speed.
摘要翻译：一种用于改变数据访问速度的缓冲区。将缓冲器与诸如双倍数据速率同步动态随机存取存储器的存储器组合，可以提高存储器系统的数据传输速率。缓冲器与控制芯片组和多个存储器模块耦合，以提供数据分析和组装的功能，以满足双向数据传输接口并获得更高的数据传输速率。缓冲器还具有隔离两侧电气连接的功能。来自存储器模块的单个信号接口可以由缓冲器转换成互补源同步信号，从而可以实现高速数据传输。存储器系统可以应用若干这样的缓冲器以实现甚至更高的数据传输速度。

6. 发明授权

US06490665B1 Memory-access management method and system for synchronous random-access memory or the like 有权
标题翻译：用于同步随机存取存储器的内存访问管理方法和系统等
公开(公告)号：US06490665B1
公开(公告)日：2002-12-03
申请号：US09350974
申请日：1999-07-09
申请人： Jiin Lai , Chih-kuo Kao , Chia-Hsin Chen
发明人： Jiin Lai , Chih-kuo Kao , Chia-Hsin Chen
IPC分类号： G06F1200
CPC分类号： G06F12/0895 , G06F12/123
摘要： A memory-access management method and system is provided for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system includes a page-table register unit including a page table for storing a predefined number of recently accessed memory locations of the memory unit. Further, the memory-page management system includes a comparison unit capable of, in response to each access request to the memory unit, checking whether the requested memory location is a hit to any one stored in the page table in the page-table register unit. A utilization-rate register unit is coupled to the page-table register unit for monitoring the least-recently-used records stored in the page-table register unit; and moreover, a validity-checking unit is coupled to the page-table register unit for checking whether the address data stored in the page table in the page-table register unit is valid or invalid.
摘要翻译：提供了一种与SDRAM（同步动态随机存取存储器）等一起使用的存储器访问管理方法和系统，用于通过跟踪存储器访问历史来增加对SDRAM的存储器访问的性能以前的访问操作。存储器页管理系统包括页表寄存器单元，其包括用于存储存储器单元的预定数量的最近访问的存储器位置的页表。此外，存储器页管理系统包括：比较单元，其能够响应于对存储器单元的每个访问请求，检查所请求的存储器位置是否是存储在页表寄存器单元中的页表中的任何一个的命中。利用率寄存器单元耦合到页表寄存器单元，用于监视存储在页表寄存器单元中的最近最少使用的记录; 此外，有效性检查单元耦合到页表寄存器单元，用于检查存储在页表寄存器单元中的页表中的地址数据是有效还是无效。

7. 发明授权

US08781332B2 Optical transceiver module, optical transmission device, and optical transmission method 有权
标题翻译：光收发模块，光传输设备和光传输方式
公开(公告)号：US08781332B2
公开(公告)日：2014-07-15
申请号：US13018548
申请日：2011-02-01
申请人： Jin-Kuan Tang , Jiin Lai
发明人： Jin-Kuan Tang , Jiin Lai
IPC分类号： H04B10/00
CPC分类号： H04B10/40
摘要： An optical transceiver module adapted to a link device includes a connection unit, a driving unit and optical transmitting and receiving units. The connection unit, to be coupled with the link device, includes an indicating element for generating an indicating signal when the connection unit is coupled with the link device. The driving unit, coupled with the connection unit, receives the indicating signal and outputs a control signal according to the indicating signal. The optical transmitting unit, coupled with the driving unit, receives the control signal for driving the optical transmitting unit to output a first optical signal. The optical receiving unit, coupled with the driving unit, transmits a received second optical signal to the driving unit. An optical transmission device using the optical transceiver module, and an optical transmission method are also disclosed. A link training sequence can be initiated after the connection unit is actually coupled with the link device. Thus, a host cannot enter a disable mode due to error connection.
摘要翻译：适于链接装置的光收发模块包括连接单元，驱动单元和光发射和接收单元。要与链接装置耦合的连接单元包括用于当连接单元与链接装置耦合时产生指示信号的指示元件。与连接单元耦合的驱动单元接收指示信号，并根据指示信号输出控制信号。与驱动单元耦合的光发送单元接收用于驱动光发送单元的控制信号以输出第一光信号。光接收单元与驱动单元耦合，将接收到的第二光信号发送到驱动单元。还公开了使用光收发模块的光传输装置和光传输方法。链路训练序列可以在连接单元实际上与链路设备耦合之后启动。因此，由于错误连接，主机无法进入禁用模式。

8. 发明授权

US08549184B2 USB transaction translator with buffers and a bulk transaction method 有权
标题翻译：具有缓冲区和批量事务方法的USB事务翻译器
公开(公告)号：US08549184B2
公开(公告)日：2013-10-01
申请号：US12959299
申请日：2010-12-02
申请人： Jinkuan Tang , Jiin Lai , Buheng Xu , Hui Jiang
发明人： Jinkuan Tang , Jiin Lai , Buheng Xu , Hui Jiang
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F13/385
摘要： The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN/OUT bulk transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. In a bulk-IN transaction, before the host sends an IN packet, the controller pre-fetches data and stores the data in the buffers until all the buffers are full or a requested data length has been achieved; the pre-fetched data are then sent to the host after the host sends the IN packet. In a bulk-OUT transaction, the controller stores the data sent from the host in the buffers, and the data are then post-written to the device.
摘要翻译：本发明涉及通用串行总线（USB）事务转换器和相关的IN / OUT批量交易方法。设备接口经由设备总线耦合到设备，并且主机接口通过主机总线耦合到主机，其中主机USB版本高于设备USB版本。配置为存储数据的至少两个缓冲器被布置在设备接口和主机接口之间。控制器交替地将数据存储在缓冲器中。在批量IN事务中，在主机发送IN数据包之前，控制器预取数据并将数据存储在缓冲器中，直到所有缓冲器已满或已达到所请求的数据长度为止; 在主机发送IN数据包之后，将预取的数据发送到主机。在bulk-OUT事务中，控制器将从主机发送的数据存储在缓冲区中，然后将数据写入设备。

9. 发明申请

US20110246681A1 APPARATUS INTEROPERABLE WITH BACKWARD COMPATIBLE OPTICAL USB DEVICE 有权
标题翻译：装置与后置兼容的OPTICAL USB DEVICE相兼容
公开(公告)号：US20110246681A1
公开(公告)日：2011-10-06
申请号：US12818342
申请日：2010-06-18
申请人： Jiin Lai
发明人： Jiin Lai
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F13/4081 , G06F2213/0042
摘要： An apparatus configured to couple to a universal serial bus (USB) 3.0 connector. The apparatus includes a management controller configured to couple to the USB 3.0 connector. The management controller is configured to detect from behavior on the D+ and D− pins of the USB 3.0 connector whether a device plugged into the USB 3.0 connector is a conventional USB 3.0 device or an optical USB device.
摘要翻译：一种被配置为耦合到通用串行总线（USB）3.0连接器的装置。该装置包括配置成耦合到USB 3.0连接器的管理控制器。管理控制器配置为检测USB 3.0连接器的D +和D-引脚上的行为，连接USB 3.0连接器的设备是传统的USB 3.0设备还是光学USB设备。

10. 发明申请

US20110219272A1 Data Transmission System and Method Thereof 有权
标题翻译：数据传输系统及其方法
公开(公告)号：US20110219272A1
公开(公告)日：2011-09-08
申请号：US12862134
申请日：2010-08-24
申请人： Jiin Lai , Buheng Xu , Jinkuan Tang
发明人： Jiin Lai , Buheng Xu , Jinkuan Tang
IPC分类号： G06F11/08 , G06F13/00 , G06F13/12
CPC分类号： G06F13/385 , G06F11/08 , G06F13/00 , G06F13/12
摘要： A data transmission system is provided. The data transmission system includes a first control circuit coupled to a first device, a translation circuit coupled to the first control circuit and a second control circuit coupled to the translation circuit. The first control circuit decodes a first format data packet sent by the first device. The translation circuit receives the decoded first format data packet and translates the decoded first format data packet into a second format data packet. The second control circuit transmits the second format data packet to a host. A data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device.
摘要翻译：提供数据传输系统。数据传输系统包括耦合到第一设备的第一控制电路，耦合到第一控制电路的平移电路和耦合到转换电路的第二控制电路。第一控制电路解码由第一设备发送的第一格式数据分组。翻译电路接收解码的第一格式数据分组，并将解码的第一格式数据分组转换为第二格式数据分组。第二控制电路将第二格式数据包发送到主机。第一设备的数据传输速率比第二设备的数据传输速率慢，并且数据传输系统向后兼容于第一设备。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式