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1. 发明授权

US06269430B1 Method for controlling a process of writing data sent by a central processing unit to a memory by using a central processing unit interface 有权
标题翻译：用于通过使用中央处理单元接口来控制将由中央处理单元发送的数据写入存储器的处理的方法
公开(公告)号：US06269430B1
公开(公告)日：2001-07-31
申请号：US09342711
申请日：1999-06-29
申请人： Chia-Hsin Chen , You-Ming Chiu , Jiin Lai
发明人： Chia-Hsin Chen , You-Ming Chiu , Jiin Lai
IPC分类号： G06F1200
CPC分类号： G06F12/0875 , G06F13/4243 , G06F2212/303
摘要： A method for a CPU interface to control a writing process that writes data sent from a CPU to a memory. The CPU interface controls the writing process through steps mainly including receiving a write request and data from a CPU, sending a dummy request to the memory control circuit of the memory circuit, and then writing the data to a memory of the memory circuit. After the CPU interface receives a write request from the CPU, the CPU interface sends a dummy request to the memory control circuit to pre-charge and activate the designative memory page of the memory circuit before the data is sent to the memory circuit. Since the designative memory page is always pre-charged and activated while the data is received at the memory control circuit, the memory control circuit sends only a write command to the memory for writing the data to the memory without further pre-charging and activating the designative memory page. Therefore, the total number of clock cycles required for processing a write request is shortened.
摘要翻译：一种CPU接口的方法，用于控制将从CPU发送到存储器的数据写入的写入过程。 CPU接口通过主要包括从CPU接收写入请求和数据，向存储器电路的存储器控制电路发送伪请求，然后将数据写入存储器电路的存储器的步骤来控制写入过程。在CPU接口从CPU接收到写请求之后，CPU接口向存储器控制电路发送伪请求，以在数据被发送到存储器电路之前对存储器电路的指定存储器页进行预充电和激活。由于在存储器控制电路中接收到数据时，指定存储器页面总是被预先充电并被激活，所以存储器控制电路仅将写入命令发送到存储器，用于将数据写入存储器，而无需进一步的预充电和激活指定记忆页面。因此，缩短了处理写请求所需的总时钟周期数。

2. 发明授权

US06278641B1 Method and apparatus capable of programmably delaying clock of DRAM 有权
标题翻译：能够可编程地延迟DRAM的时钟的方法和装置
公开(公告)号：US06278641B1
公开(公告)日：2001-08-21
申请号：US09578234
申请日：2000-05-24
申请人： Chia-Hsin Chen , Jiin Lai
发明人： Chia-Hsin Chen , Jiin Lai
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , G11C11/4076
摘要： An apparatus and method capable of programmably delaying a clock of a memory. The apparatus and method utilize the BIOS, external electric switches or other logic devices to selectively delay the clock of the DRAM and/or the internal clock of the north bridge, by which the DRAM has enough setup time at the rising edge of work clock to correctly read out the command word. The north bridge can then correctly receive data from the DRAM module and transfer the data to the CPU or AGP. Therefore, the memory can function normally even if the memory is operated at high speed or with heavy loading.
摘要翻译：一种能够可编程地延迟存储器的时钟的装置和方法。该装置和方法利用BIOS，外部电气开关或其他逻辑装置来选择性地延迟DRAM的时钟和/或北桥的内部时钟，由此DRAM在工作时钟的上升沿具有足够的建立时间正确读出命令字。然后，北桥可以从DRAM模块正确接收数据，并将数据传输到CPU或AGP。因此，即使存储器以高速或大负载运行，存储器也能正常工作。

3. 发明授权

US06738880B2 Buffer for varying data access speed and system applying the same 有权
标题翻译：用于变化数据访问速度的缓冲器和应用它的系统
公开(公告)号：US06738880B2
公开(公告)日：2004-05-18
申请号：US09878896
申请日：2001-06-11
申请人： Jiin Lai , Chia-Hsin Chen , Nai-Shung Chang
发明人： Jiin Lai , Chia-Hsin Chen , Nai-Shung Chang
IPC分类号： G06F1300
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be enhanced. The buffer is coupled with a control chip set and several memory modules to provide functions of data analysis and assembly to satisfy a two-way data transmission interface and to obtain a higher data transmission rate. The buffer also has the function of isolating the electric connection between two sides. A single signal interface from a memory module can be converted to a complementary source synchronous signal by the buffer, so that a high-speed data transmission can be achieved. A memory system can apply several of such buffers to achieve an even higher data transmission speed.
摘要翻译：一种用于改变数据访问速度的缓冲区。将缓冲器与诸如双倍数据速率同步动态随机存取存储器的存储器组合，可以提高存储器系统的数据传输速率。缓冲器与控制芯片组和多个存储器模块耦合，以提供数据分析和组装的功能，以满足双向数据传输接口并获得更高的数据传输速率。缓冲器还具有隔离两侧电气连接的功能。来自存储器模块的单个信号接口可以由缓冲器转换成互补源同步信号，从而可以实现高速数据传输。存储器系统可以应用若干这样的缓冲器以实现甚至更高的数据传输速度。

4. 发明授权

US06490665B1 Memory-access management method and system for synchronous random-access memory or the like 有权
标题翻译：用于同步随机存取存储器的内存访问管理方法和系统等
公开(公告)号：US06490665B1
公开(公告)日：2002-12-03
申请号：US09350974
申请日：1999-07-09
申请人： Jiin Lai , Chih-kuo Kao , Chia-Hsin Chen
发明人： Jiin Lai , Chih-kuo Kao , Chia-Hsin Chen
IPC分类号： G06F1200
CPC分类号： G06F12/0895 , G06F12/123
摘要： A memory-access management method and system is provided for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system includes a page-table register unit including a page table for storing a predefined number of recently accessed memory locations of the memory unit. Further, the memory-page management system includes a comparison unit capable of, in response to each access request to the memory unit, checking whether the requested memory location is a hit to any one stored in the page table in the page-table register unit. A utilization-rate register unit is coupled to the page-table register unit for monitoring the least-recently-used records stored in the page-table register unit; and moreover, a validity-checking unit is coupled to the page-table register unit for checking whether the address data stored in the page table in the page-table register unit is valid or invalid.
摘要翻译：提供了一种与SDRAM（同步动态随机存取存储器）等一起使用的存储器访问管理方法和系统，用于通过跟踪存储器访问历史来增加对SDRAM的存储器访问的性能以前的访问操作。存储器页管理系统包括页表寄存器单元，其包括用于存储存储器单元的预定数量的最近访问的存储器位置的页表。此外，存储器页管理系统包括：比较单元，其能够响应于对存储器单元的每个访问请求，检查所请求的存储器位置是否是存储在页表寄存器单元中的页表中的任何一个的命中。利用率寄存器单元耦合到页表寄存器单元，用于监视存储在页表寄存器单元中的最近最少使用的记录; 此外，有效性检查单元耦合到页表寄存器单元，用于检查存储在页表寄存器单元中的页表中的地址数据是有效还是无效。

5. 发明申请

US20090172264A1 SYSTEM AND METHOD OF INTEGRATING DATA ACCESSING COMMANDS 审中-公开
标题翻译：集成数据访问命令的系统和方法
公开(公告)号：US20090172264A1
公开(公告)日：2009-07-02
申请号：US12238152
申请日：2008-09-25
申请人： Chien-Ping Chung , Chia-Hsin Chen , Ming-Che Liu
发明人： Chien-Ping Chung , Chia-Hsin Chen , Ming-Che Liu
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0679 , G06F12/0246
摘要： A data accessing command integration method includes the following steps. Firstly, M data accessing commands are sequentially received through a bus, wherein N data accessing commands contained in the M data accessing commands have the same command type and comply with a sequential address relationship. Next, the N data accessing commands are re-ordered according to the addressing sequence, so that a first data corresponding to the re-ordered N data accessing commands are sequentially accessed in the data memory.
摘要翻译：数据访问命令集成方法包括以下步骤。首先，通过总线顺序地接收M个数据访问命令，其中包含在M个数据访问命令中的N个数据访问命令具有相同的命令类型并且遵循顺序地址关系。接下来，根据寻址序列重新排序N个数据访问命令，从而在数据存储器中顺序地访问对应于重新排序的N个数据访问命令的第一数据。

6. 发明授权

US06446172B1 Method and system for controlling the memory access operation performed by a central processing unit in a computer system 有权
标题翻译：用于控制由计算机系统中的中央处理单元执行的存储器访问操作的方法和系统
公开(公告)号：US06446172B1
公开(公告)日：2002-09-03
申请号：US09335602
申请日：1999-06-18
申请人： Chia-Hsin Chen , Nai-Shung Chang
发明人： Chia-Hsin Chen , Nai-Shung Chang
IPC分类号： G06F1208
CPC分类号： G06F12/0859 , G06F13/161
摘要： A memory access control method and system is provided for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner than the prior art. This memory access control method and system is characterized by, for each read request from the CPU, the prompt transfer of the corresponding internal read-request signal to the memory control unit, right after it is issued and without waiting until the CPU issues the L1 write-back signal of the current read request. If the current read request is a hit to the cache memory, a read-stop signal is promptly issued to stop the current read operation on the memory unit, and then a cache write-back operation is performed to write the cache data back into the memory unit. This method and system can help reduce the period of waiting states by the CPU, thus increasing the overall memory access performance by the CPU and the overall system performance of the computer system.
摘要翻译：提供存储器访问控制方法和系统，用于在计算机系统上以比现有技术更有效的方式将中央处理单元（CPU）的存储器访问操作控制到存储器单元。这种存储器访问控制方法和系统的特征在于，对于来自CPU的每个读取请求，在相应的内部读取请求信号被发出之后立即将其传送到存储器控制单元，并且不等待直到CPU发出L1 当前读取请求的回写信号。如果当前读取请求是对高速缓存存储器的命中，则立即发出读停止信号以停止对存储器单元的当前读取操作，然后执行高速缓存回写操作以将高速缓存数据写回到存储单元该方法和系统可以帮助减少CPU等待状态的时间，从而提高CPU的整体内存访问性能以及计算机系统的整体系统性能。

7. 发明授权

US09104546B2 Method for performing block management using dynamic threshold, and associated memory device and controller thereof 有权
标题翻译：使用动态阈值执行块管理的方法，以及相关联的存储器件及其控制器
公开(公告)号：US09104546B2
公开(公告)日：2015-08-11
申请号：US13014735
申请日：2011-01-27
申请人： Chi-Lung Wang , Chia-Hsin Chen , Chien-Cheng Lin
发明人： Chi-Lung Wang , Chia-Hsin Chen , Chien-Cheng Lin
IPC分类号： G06F13/12 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/10 , G06F2212/7201
摘要： A method for performing block management is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: adjusting a dynamic threshold according to at least one condition; and comparing a valid/invalid page count of a specific block of the plurality of blocks with the dynamic threshold to determine whether to erase the specific block. An associated memory device and a controller thereof are also provided, where the memory device includes the Flash memory and the controller. In particular, the controller includes a read only memory (ROM) arranged to store a program code, and further includes a microprocessor arranged to execute the program code to control access to the Flash memory and manage the plurality of blocks, where under control of the microprocessor, the controller operates according to the method.
摘要翻译：提供了一种执行块管理的方法。该方法应用于闪速存储器的控制器，其中闪速存储器包括多个块。该方法包括：根据至少一个条件调整动态阈值; 以及将所述多个块中的特定块的有效/无效页面计数与所述动态阈值进行比较，以确定是否擦除所述特定块。还提供了一种相关联的存储器件及其控制器，其中存储器件包括闪存和控制器。特别地，控制器包括被布置为存储程序代码的只读存储器（ROM），并且还包括微处理器，其被布置为执行程序代码以控制对闪存的访问并管理多个块，其中在微处理器，控制器根据方法进行操作。

8. 发明授权

US08195870B2 Memory card and method for handling data updating of a flash memory 有权
标题翻译：用于处理闪存的数据更新的存储卡和方法
公开(公告)号：US08195870B2
公开(公告)日：2012-06-05
申请号：US12050205
申请日：2008-03-18
申请人： Chia-Hsin Chen
发明人： Chia-Hsin Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block.
摘要翻译：本发明提供了一种处理闪速存储器的数据更新的方法。在一个实施例中，闪速存储器包括母块，其包括要更新的多个更新的页面。首先，将不记录数据的备用块作为与母块对应的文件分配表（FAT）块而弹出。然后将用于更新母块的更新页面的数据写入FAT块的多个替换页面。最后，替换页面和更新页面之间的多个映射关系被记录在存储在FAT块中的页面映射表中。

9. 发明申请

US20090248965A1 HYBRID FLASH MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开
标题翻译：混合闪速存储器装置及其控制方法
公开(公告)号：US20090248965A1
公开(公告)日：2009-10-01
申请号：US12401466
申请日：2009-03-10
申请人： Yuan-Huei Lee , Chi Chang , Chia-Hsin Chen , Ming-Che Liu
发明人： Yuan-Huei Lee , Chi Chang , Chia-Hsin Chen , Ming-Che Liu
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7208
摘要： A hybrid flash memory device and a control method of the hybrid flash memory device are provided. The hybrid flash memory device includes a micro controller connected to a host bus for receiving data to be written in the hybrid flash memory device from a host via the host bus; and a memory module coupled to the micro controller. The flash module includes a first type of flash memory and a second type of flash memory. The data are determined to be written in a first log block of the first type of flash memory when the data size is not greater than a predetermined data size. On the contrary, the data are determined to be written in a second log block of the second type of flash memory when the data size is greater than the predetermined data size.
摘要翻译：提供一种混合式闪速存储装置和混合式闪速存储装置的控制方法。混合式闪速存储装置包括连接到主机总线的微控制器，用于经由主机总线从主机接收要写入混合式闪速存储器装置的数据; 以及耦合到所述微控制器的存储器模块。闪存模块包括第一类型的闪存和第二类闪存。当数据大小不大于预定数据大小时，数据被确定为被写入第一类闪速存储器的第一对数块中。相反，当数据大小大于预定数据大小时，确定数据被写入第二类闪存的第二对数块中。

10. 发明申请

US20080288818A1 Method and System for Protecting Information between a Master Terminal and a Slave Terminal 审中-公开
标题翻译：主终端和从站之间的信息保护方法和系统
公开(公告)号：US20080288818A1
公开(公告)日：2008-11-20
申请号：US12030209
申请日：2008-02-13
申请人： Wen-Yueh Lai , Chia-Hsin Chen
发明人： Wen-Yueh Lai , Chia-Hsin Chen
IPC分类号： G06F11/07
CPC分类号： G06F1/305 , G06F3/14 , G09G2330/02 , G09G2330/08
摘要： In an application system of a liquid crystal display, for protecting transmissions between a master terminal and a slave terminal, effects caused by an unstable power source of the slave terminal have to be reduced to a lowest degree. When the application system is reset or under normal operations with the power source having a suddenly-decreased or suddenly-unstable voltage level, the transmission between the master terminal and the slave terminal have to be terminated, and related data of the terminated transmission is temporarily stored. When the voltage of the slave terminal is confirmed to reach to a stable voltage over a predetermined duration, the transmission may be restored by the stored data.
摘要翻译：在液晶显示器的应用系统中，为了保护主终端和从属终端之间的传输，必须将从属终端的不稳定电源引起的影响降低到最低程度。当应用系统复位或正常工作时，电源突然降低或突然不稳定的电压电平，主终端和从终端之间的传输必须终止，终止传输的相关数据暂时存储。当确定从站终端的电压在预定时间内达到稳定的电压时，可以通过存储的数据恢复传输。

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