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1. 发明授权

US08609479B2 Gated-varactors 有权
标题翻译：门控变容二极管
公开(公告)号：US08609479B2
公开(公告)日：2013-12-17
申请号：US13595667
申请日：2012-08-27
申请人： Chia-Chung Chen , Chewn-Pu Jou , Chin Wei Kuo , Sally Liu
发明人： Chia-Chung Chen , Chewn-Pu Jou , Chin Wei Kuo , Sally Liu
IPC分类号： H01L21/02
CPC分类号： H01L29/93 , H01L29/7391 , H01L29/94
摘要： In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region.
摘要翻译：在至少一个实施例中，制造变容二极管的方法包括在衬底上形成阱。该井具有第一种掺杂。在阱中形成第一源极区域和第二源极区域，并且第一源极区域和第二源极区域具有第二类型掺杂。在阱中形成漏极区，漏区具有第一类掺杂。在漏极区域和第一源极区域之间的阱上形成第一栅极区域。此外，在漏极区域和第二源极区域之间的阱之上形成第二栅极区域。

2. 发明授权

US08273616B2 Gated-varactors 有权
标题翻译：门控变容二极管
公开(公告)号：US08273616B2
公开(公告)日：2012-09-25
申请号：US12708603
申请日：2010-02-19
申请人： Chia-Chung Chen , Chewn-Pu Jou , Chin-Wei Kuo , Sally Liu
发明人： Chia-Chung Chen , Chewn-Pu Jou , Chin-Wei Kuo , Sally Liu
IPC分类号： H01L21/00
CPC分类号： H01L29/93 , H01L29/7391 , H01L29/94
摘要： Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed.
摘要翻译：本发明的各种实施例提供了一种变容二极管结构，其取决于配置，可以提供基于反向偏置结电容器，沟道电容器和氧化物电容器中的一个或其组合的C-V特性。结电容器通过反向偏置P +源极区域和N阱来形成。在P +源极区域和N +漏极区域之间形成沟道电容，并且在栅极氧化物区域形成氧化物电容器。取决于偏压栅极电压VG，源极电压VS和漏极电压VD的一个或组合，实施例可以利用上述电容器中的一个或组合。还公开了在压控振荡器（VCO）中使用变容二极管的其它实施例。

3. 发明申请

US20110204969A1 GATED-VARACTORS 有权
标题翻译：浇口式变送器
公开(公告)号：US20110204969A1
公开(公告)日：2011-08-25
申请号：US12708603
申请日：2010-02-19
申请人： Chia-Chung CHEN , Chewn-Pu Jou , Chin Wei Kuo , Sally Liu
发明人： Chia-Chung CHEN , Chewn-Pu Jou , Chin Wei Kuo , Sally Liu
IPC分类号： H01G7/00 , H01L21/329 , H01L29/93
CPC分类号： H01L29/93 , H01L29/7391 , H01L29/94
摘要： Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed.
摘要翻译：本发明的各种实施例提供了一种变容二极管结构，其取决于配置，可以提供基于反向偏置结电容器，沟道电容器和氧化物电容器中的一个或其组合的C-V特性。结电容器通过反向偏置P +源极区域和N阱来形成。在P +源极区域和N +漏极区域之间形成沟道电容，并且在栅极氧化物区域形成氧化物电容器。取决于偏压栅极电压VG，源极电压VS和漏极电压VD的一个或组合，实施例可以利用上述电容器中的一个或组合。还公开了在压控振荡器（VCO）中使用变容二极管的其它实施例。

4. 发明授权

US08928127B2 Noise decoupling structure with through-substrate vias 有权
标题翻译：带通孔的噪声去耦结构
公开(公告)号：US08928127B2
公开(公告)日：2015-01-06
申请号：US12889650
申请日：2010-09-24
申请人： Chia-Chung Chen , Chewn-Pu Jou , Sally Liu
发明人： Chia-Chung Chen , Chewn-Pu Jou , Sally Liu
IPC分类号： H01L23/552 , H01L23/58
CPC分类号： H01L23/66 , H01L21/76224 , H01L21/76898 , H01L23/481 , H01L23/585 , H01L29/0619 , H01L2223/6616 , H01L2223/6666 , H01L2924/0002 , H01L2924/00
摘要： A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate.
摘要翻译：一种装置包括具有前表面和后表面的基板; 在基板的前表面上的集成电路器件; 以及在所述基板的背面上的金属板，其中，所述金属板与所述集成电路器件的整体重叠。保护环延伸到基板中并且环绕集成电路装置。保护环由导电材料形成。贯穿基板通孔（TSV）穿透基板并与金属板电耦合。

5. 发明申请

US20120074515A1 Noise Decoupling Structure with Through-Substrate Vias 有权
标题翻译：噪声去耦结构与通孔通孔
公开(公告)号：US20120074515A1
公开(公告)日：2012-03-29
申请号：US12889650
申请日：2010-09-24
申请人： Chia-Chung Chen , Chewn-Pu Jou , Sally Liu
发明人： Chia-Chung Chen , Chewn-Pu Jou , Sally Liu
IPC分类号： H01L29/08
CPC分类号： H01L23/66 , H01L21/76224 , H01L21/76898 , H01L23/481 , H01L23/585 , H01L29/0619 , H01L2223/6616 , H01L2223/6666 , H01L2924/0002 , H01L2924/00
摘要： A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate.
摘要翻译：一种装置包括具有前表面和后表面的基板; 在基板的前表面上的集成电路器件; 以及在所述基板的背面上的金属板，其中所述金属板与所述集成电路器件的整体重叠。保护环延伸到基板中并且环绕集成电路装置。保护环由导电材料形成。贯穿基板通孔（TSV）穿透基板并与金属板电耦合。

6. 发明授权

US08373229B2 Gate controlled bipolar junction transistor on fin-like field effect transistor (FinFET) structure 有权
标题翻译：鳍状场效应晶体管（FinFET）结构的栅极控制双极结晶体管
公开(公告)号：US08373229B2
公开(公告)日：2013-02-12
申请号：US12871476
申请日：2010-08-30
申请人： Chia-Chung Chen , Chewn-Pu Jou , Feng Yuan , Sally Liu
发明人： Chia-Chung Chen , Chewn-Pu Jou , Feng Yuan , Sally Liu
IPC分类号： H01L27/02
CPC分类号： H01L27/1211 , H01L29/66265 , H01L29/7317 , H01L29/785
摘要： An integrated circuit device is disclosed. An exemplary integrated circuit device includes: a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over the base portion of the fin structure. The collector portion is a first doped region including a first type dopant, and is coupled with a first terminal for electrically biasing the collector portion. The emitter portion is a second doped region including the first type dopant, and is coupled with a second terminal for electrically biasing the emitter portion. The base portion is a third doped region including a second type dopant opposite the first type, and is coupled with a third terminal for electrically biasing the base portion. The gate structure is coupled with a fourth terminal for electrically biasing the gate structure, such that the gate structure controls a path of current through the base portion.
摘要翻译：公开了一种集成电路器件。示例性的集成电路器件包括：半导体衬底; 翅片结构，设置在所述半导体衬底上; 以及设置在所述翅片结构的基部上的栅极结构。集电极部分是包括第一类型掺杂剂的第一掺杂区域，并且与用于电偏置集电极部分的第一端子耦合。发射极部分是包括第一类型掺杂剂的第二掺杂区域，并且与用于电偏置发射极部分的第二端子耦合。基极部分是包括与第一类型相反的第二类型掺杂物的第三掺杂区域，并且与用于电偏置基极部分的第三端子耦合。栅极结构与用于电偏置栅极结构的第四端子耦合，使得栅极结构控制电流通过基极部分的路径。

7. 发明申请

US20120049282A1 GATE CONTROLLED BIPOLAR JUNCTION TRANSISTOR ON FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) STRUCTURE 有权
标题翻译：晶体管效应晶体管（FINFET）结构上的栅极控制双极晶体管
公开(公告)号：US20120049282A1
公开(公告)日：2012-03-01
申请号：US12871476
申请日：2010-08-30
申请人： Chia-Chung Chen , Chewn-Pu Jou , Feng Yuan , Sally Liu
发明人： Chia-Chung Chen , Chewn-Pu Jou , Feng Yuan , Sally Liu
IPC分类号： H01L27/12
CPC分类号： H01L27/1211 , H01L29/66265 , H01L29/7317 , H01L29/785
摘要： An integrated circuit device is disclosed. An exemplary integrated circuit device includes: a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over the base portion of the fin structure. The collector portion is a first doped region including a first type dopant, and is coupled with a first terminal for electrically biasing the collector portion. The emitter portion is a second doped region including the first type dopant, and is coupled with a second terminal for electrically biasing the emitter portion. The base portion is a third doped region including a second type dopant opposite the first type, and is coupled with a third terminal for electrically biasing the base portion. The gate structure is coupled with a fourth terminal for electrically biasing the gate structure, such that the gate structure controls a path of current through the base portion.
摘要翻译：公开了一种集成电路器件。示例性的集成电路器件包括：半导体衬底; 翅片结构，设置在所述半导体衬底上; 以及设置在所述翅片结构的基部上的栅极结构。集电极部分是包括第一类型掺杂剂的第一掺杂区域，并且与用于电偏置集电极部分的第一端子耦合。发射极部分是包括第一类型掺杂剂的第二掺杂区域，并且与用于电偏置发射极部分的第二端子耦合。基极部分是包括与第一类型相反的第二类型掺杂物的第三掺杂区域，并且与用于电偏置基极部分的第三端子耦合。栅极结构与用于电偏置栅极结构的第四端子耦合，使得栅极结构控制电流通过基极部分的路径。

8. 发明授权

US08115280B2 Four-terminal gate-controlled LVBJTs 有权
标题翻译：四端门控LVBJT
公开(公告)号：US08115280B2
公开(公告)日：2012-02-14
申请号：US12715071
申请日：2010-03-01
申请人： Chia-Chung Chen , Shuo-Mao Chen , Chin-Wei Kuo , Sally Liu
发明人： Chia-Chung Chen , Shuo-Mao Chen , Chin-Wei Kuo , Sally Liu
IPC分类号： H01L29/735 , H01L29/732
CPC分类号： H01L21/8224 , H01L27/0207 , H01L27/0821 , H01L27/1203 , H01L27/1214 , H01L29/0692 , H01L29/735
摘要： An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.
摘要翻译：集成电路结构包括第一导电类型的阱区域，在阱区域上与第一导电类型相反的第二导电类型的发射极，在阱区域上的基本上环绕发射极的第二导电类型的集电极，以及第一导电类型在阱区上的基极接触。基座接触件通过收集器与发射器水平间隔开。至少一个导电条水平地将发射器，集电器和基座接触件彼此分开间隔开。电介质层直接位于至少一个导电带的下面并与其接触。

9. 发明申请

US20100219504A1 Four-Terminal Gate-Controlled LVBJTs 有权
标题翻译：四端门控LVBJT
公开(公告)号：US20100219504A1
公开(公告)日：2010-09-02
申请号：US12715071
申请日：2010-03-01
申请人： Chia-Chung Chen , Shuo-Mao Chen , Chin-Wei Kuo , Sally Liu
发明人： Chia-Chung Chen , Shuo-Mao Chen , Chin-Wei Kuo , Sally Liu
IPC分类号： H01L29/735
CPC分类号： H01L21/8224 , H01L27/0207 , H01L27/0821 , H01L27/1203 , H01L27/1214 , H01L29/0692 , H01L29/735
摘要： An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.
摘要翻译：集成电路结构包括第一导电类型的阱区域，在阱区域上与第一导电类型相反的第二导电类型的发射极，在阱区域上的基本上环绕发射极的第二导电类型的集电极，以及第一导电类型在阱区上的基极接触。基座接触件通过收集器与发射器水平间隔开。至少一个导电条水平地将发射器，集电器和基座接触件彼此分开间隔开。电介质层直接位于至少一个导电带的下面并与其接触。

10. 发明申请

US20110265051A1 Method for Substrate Noise Analysis 有权
标题翻译：基板噪声分析方法
公开(公告)号：US20110265051A1
公开(公告)日：2011-10-27
申请号：US12766732
申请日：2010-04-23
申请人： Tzu-Jin Yeh , Kal-Wen Tan , Chewn-Pu Jou , Sally Liu , Fu-Lung Hsueh
发明人： Tzu-Jin Yeh , Kal-Wen Tan , Chewn-Pu Jou , Sally Liu , Fu-Lung Hsueh
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.
摘要翻译：根据实施例，用于衬底噪声分析的方法包括使用基于第一处理器的系统，创建和模拟包括晶体管的多端子模型的电路原理图，然后基于电路原理图中所示的特性创建布局和仿真结果的模拟。多端子模型包括源极端子，栅极端子，漏极端子，主体端子和保护环端子。

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