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1. 发明授权

US08273616B2 Gated-varactors 有权
标题翻译：门控变容二极管
公开(公告)号：US08273616B2
公开(公告)日：2012-09-25
申请号：US12708603
申请日：2010-02-19
申请人： Chia-Chung Chen , Chewn-Pu Jou , Chin-Wei Kuo , Sally Liu
发明人： Chia-Chung Chen , Chewn-Pu Jou , Chin-Wei Kuo , Sally Liu
IPC分类号： H01L21/00
CPC分类号： H01L29/93 , H01L29/7391 , H01L29/94
摘要： Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed.
摘要翻译：本发明的各种实施例提供了一种变容二极管结构，其取决于配置，可以提供基于反向偏置结电容器，沟道电容器和氧化物电容器中的一个或其组合的C-V特性。结电容器通过反向偏置P +源极区域和N阱来形成。在P +源极区域和N +漏极区域之间形成沟道电容，并且在栅极氧化物区域形成氧化物电容器。取决于偏压栅极电压VG，源极电压VS和漏极电压VD的一个或组合，实施例可以利用上述电容器中的一个或组合。还公开了在压控振荡器（VCO）中使用变容二极管的其它实施例。

2. 发明授权

US08946832B2 Filter using a waveguide structure 有权
标题翻译：使用波导结构滤波
公开(公告)号：US08946832B2
公开(公告)日：2015-02-03
申请号：US12701170
申请日：2010-02-05
申请人： Chia-Chung Chen , Chewn-Pu Jou , Chin-Wei Kuo
发明人： Chia-Chung Chen , Chewn-Pu Jou , Chin-Wei Kuo
IPC分类号： H01L29/84 , H01P1/203
CPC分类号： H01P1/20345
摘要： A representative filter comprises a silicon-on-insulator substrate having a top surface, a metal shielding positioned above the top surface of the silicon-on-insulator substrate, and a band-pass filter device positioned above the metal shielding. The band-pass filter device includes a first port, a second port, and a coupling metal positioned between the first and second ports.
摘要翻译：代表性滤波器包括具有顶表面的绝缘体上硅衬底，位于绝缘体上硅衬底的顶表面上方的金属屏蔽以及位于金属屏蔽上方的带通滤波器器件。带通滤波器装置包括位于第一和第二端口之间的第一端口，第二端口和耦合金属。

3. 发明授权

US08115280B2 Four-terminal gate-controlled LVBJTs 有权
标题翻译：四端门控LVBJT
公开(公告)号：US08115280B2
公开(公告)日：2012-02-14
申请号：US12715071
申请日：2010-03-01
申请人： Chia-Chung Chen , Shuo-Mao Chen , Chin-Wei Kuo , Sally Liu
发明人： Chia-Chung Chen , Shuo-Mao Chen , Chin-Wei Kuo , Sally Liu
IPC分类号： H01L29/735 , H01L29/732
CPC分类号： H01L21/8224 , H01L27/0207 , H01L27/0821 , H01L27/1203 , H01L27/1214 , H01L29/0692 , H01L29/735
摘要： An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.
摘要翻译：集成电路结构包括第一导电类型的阱区域，在阱区域上与第一导电类型相反的第二导电类型的发射极，在阱区域上的基本上环绕发射极的第二导电类型的集电极，以及第一导电类型在阱区上的基极接触。基座接触件通过收集器与发射器水平间隔开。至少一个导电条水平地将发射器，集电器和基座接触件彼此分开间隔开。电介质层直接位于至少一个导电带的下面并与其接触。

4. 发明申请

US20100219504A1 Four-Terminal Gate-Controlled LVBJTs 有权
标题翻译：四端门控LVBJT
公开(公告)号：US20100219504A1
公开(公告)日：2010-09-02
申请号：US12715071
申请日：2010-03-01
申请人： Chia-Chung Chen , Shuo-Mao Chen , Chin-Wei Kuo , Sally Liu
发明人： Chia-Chung Chen , Shuo-Mao Chen , Chin-Wei Kuo , Sally Liu
IPC分类号： H01L29/735
CPC分类号： H01L21/8224 , H01L27/0207 , H01L27/0821 , H01L27/1203 , H01L27/1214 , H01L29/0692 , H01L29/735
摘要： An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.
摘要翻译：集成电路结构包括第一导电类型的阱区域，在阱区域上与第一导电类型相反的第二导电类型的发射极，在阱区域上的基本上环绕发射极的第二导电类型的集电极，以及第一导电类型在阱区上的基极接触。基座接触件通过收集器与发射器水平间隔开。至少一个导电条水平地将发射器，集电器和基座接触件彼此分开间隔开。电介质层直接位于至少一个导电带的下面并与其接触。

5. 发明授权

US09087840B2 Slot-shielded coplanar strip-line compatible with CMOS processes 有权
标题翻译：与CMOS工艺兼容的插槽屏蔽共面带状线
公开(公告)号：US09087840B2
公开(公告)日：2015-07-21
申请号：US12917285
申请日：2010-11-01
申请人： Yu-Ling Lin , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chin-Wei Kuo , Chewn-Pu Jou
发明人： Yu-Ling Lin , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chin-Wei Kuo , Chewn-Pu Jou
IPC分类号： H01L23/14 , H01L23/522 , H01L23/66 , H01L27/06
CPC分类号： H01L23/5225 , H01L23/5226 , H01L23/528 , H01L23/64 , H01L23/66 , H01L27/0629 , H01L2223/6627 , H01L2924/0002 , H01L2924/00
摘要： A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.
摘要翻译：带状线包括在衬底上延伸穿过多个电介质层的接地平面; 在基板上并在接地平面的一侧的信号线; 在信号线下方和第一金属层中的第一多个金属条，其中所述第一多个金属条彼此平行并且彼此间隔开; 以及信号线下方的第二多个金属条，并且在第一金属层上方的第二金属层中。第二多个金属带垂直地与空间重叠。第一多个金属条通过接地平面电耦合到第二多个金属条，并且不通过物理地接触第一多个金属条和第二多个金属条。

6. 发明授权

US09923101B2 Semiconductor structure 有权
公开(公告)号：US09923101B2
公开(公告)日：2018-03-20
申请号：US13615503
申请日：2012-09-13
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Chewn-Pu Jou , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Chewn-Pu Jou , Min-Chie Jeng
IPC分类号： H01L29/94 , H01L29/66 , H01L21/66 , H01L27/06 , H01L49/02 , H01L23/48 , H01L23/58
CPC分类号： H01L29/94 , H01L22/34 , H01L23/481 , H01L23/585 , H01L27/0629 , H01L28/60 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.

7. 发明申请

US20120104575A1 Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes 有权
标题翻译： Slot-Shielded Coplanar Strip-line兼容CMOS工艺
公开(公告)号：US20120104575A1
公开(公告)日：2012-05-03
申请号：US12917285
申请日：2010-11-01
申请人： Yu-Ling Lin , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chin-Wei Kuo , Chewn-Pu Jou
发明人： Yu-Ling Lin , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chin-Wei Kuo , Chewn-Pu Jou
IPC分类号： H01L23/14
CPC分类号： H01L23/5225 , H01L23/5226 , H01L23/528 , H01L23/64 , H01L23/66 , H01L27/0629 , H01L2223/6627 , H01L2924/0002 , H01L2924/00
摘要： A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.
摘要翻译：带状线包括在衬底上延伸穿过多个电介质层的接地平面; 在基板上并在接地平面的一侧的信号线; 在信号线下方和第一金属层中的第一多个金属条，其中所述第一多个金属条彼此平行并且彼此间隔开; 以及信号线下方的第二多个金属条，并且在第一金属层上方的第二金属层中。第二多个金属带垂直地与空间重叠。第一多个金属条通过接地平面电耦合到第二多个金属条，并且不通过物理地接触第一多个金属条和第二多个金属条。

8. 发明授权

US08471358B2 3D inductor and transformer 有权
标题翻译： 3D电感和变压器
公开(公告)号：US08471358B2
公开(公告)日：2013-06-25
申请号：US12791705
申请日：2010-06-01
申请人： Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
发明人： Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
IPC分类号： H01L27/08
CPC分类号： H01L23/5227 , H01F17/0013 , H01F27/2804 , H01L23/49822 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/15321 , H01L2924/00 , H01L2224/0401
摘要： In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
摘要翻译：根据实施例，半导体器件包括半导体管芯，插入件和将半导体管芯接合到插入件的导电凸块。半导体管芯包括第一金属化层，第一金属化层包括第一导电图案。插入器包括第二金属化层，并且第二金属化层包括第二导电图案。一些导电凸块将第一导电图案电耦合到第二导电图案以形成线圈。其他实施例考虑了线圈，电感器和/或变压器的其他配置，并考虑了制造方法。

9. 发明授权

US08362591B2 Integrated circuits and methods of forming the same 有权
标题翻译：集成电路及其形成方法
公开(公告)号：US08362591B2
公开(公告)日：2013-01-29
申请号：US12795734
申请日：2010-06-08
申请人： Hsiao-Tsung Yen , Hsien-Pin Hu , Jhe-Ching Lu , Chin-Wei Kuo , Ming-Fa Chen , Sally Liu
发明人： Hsiao-Tsung Yen , Hsien-Pin Hu , Jhe-Ching Lu , Chin-Wei Kuo , Ming-Fa Chen , Sally Liu
IPC分类号： H01L29/93
CPC分类号： H01L27/016 , H01L29/93
摘要： A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.
摘要翻译：三维集成电路包括半导体衬底，其中衬底具有延伸穿过衬底的第一表面和第二表面的开口，并且其中第一表面和第二表面是与衬底相对的表面。导电材料基本上填充衬底的开口以形成导电的通过衬底通孔（TSV）。有源电路设置在衬底的第一表面上，电感器设置在衬底的第二表面上，并且TSV电耦合到有源电路和电感器。三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管，使得导电材料邻近介电层设置，以及设置在TSV周围的杂质注入区域，使得介电层形成在杂质注入区和TSV。

10. 发明授权

US08502338B2 Through-substrate via waveguides 有权
标题翻译：通过波导通过基板
公开(公告)号：US08502338B2
公开(公告)日：2013-08-06
申请号：US12878803
申请日：2010-09-09
申请人： Hsiao-Tsung Yen , Hsien-Pin Hu , Chin-Wei Kuo , Sally Liu
发明人： Hsiao-Tsung Yen , Hsien-Pin Hu , Chin-Wei Kuo , Sally Liu
IPC分类号： H01L29/00
CPC分类号： H01L27/0296 , H01L21/76898 , H01L23/481 , H01L23/60 , H01L29/861 , H01L2223/6622 , H01L2224/13023 , H01L2224/13025 , H01L2224/13027 , H01L2224/131 , H01L2224/14181 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014
摘要： A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.
摘要翻译：一种器件包括第一导电类型的半导体衬底，其中半导体衬底包括与第一表面相对的第一表面和第二表面。贯穿基板通孔（TSV）从半导体基板的第一表面延伸到第二表面。与第一导电类型相反的第二导电类型的阱区域包围TSV，并且从半导体衬底的第一表面延伸到第二表面。

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