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1. 发明申请

US20070030590A1 Sliding module and its axle structure 失效
标题翻译：滑动模块及其轴结构
公开(公告)号：US20070030590A1
公开(公告)日：2007-02-08
申请号：US11500102
申请日：2006-08-07
申请人： Chia-Cheng Chen , Chung Chen , Hua Hsu
发明人： Chia-Cheng Chen , Chung Chen , Hua Hsu
IPC分类号： G11B17/04
CPC分类号： H05K5/0204 , H04M1/0212 , H04M1/0237
摘要： A sliding module comprises a sliding member having a transversal plate disposed transversally and coupled vertically at a substantially middle position of two sliding plates, and the transversal plate includes a rectangular transversal groove, and the transversal groove includes a through hole disposed at an external side of the transversal groove; a spindle member being a rectangular spindle plate and includes a spindle hole disposed separately on both sides of the spindle member, and a spindle bolt passes through one of said spindle holes and is coupled to the transversal groove; a tension spring with both ends separately including a spring hook and one of the spring hooks is latched into the through hole, and another spring hook is latched into a bolt aperture of a spindle bolt above the transversal groove; and a slid member being a driven plate with both lateral sides bent into a sliding groove for embedding an external side of the sliding plate, and the driven plate includes a plate aperture for passing a spindle bolt through another spindle hole and coupling the spindle bolt; thereby, the tension spring stores energy if pushed, and the slid member continues sliding all the way to a position of releasing energy after the slid member is pushed more than half of the traveling path. The sliding module further connects an axle structure, and the axle structure comprises a vertical first pivotal axle and a horizontal second pivotal axle, and by means of the installation of the two pivotal axles, the sliding module provides the multi-directional pivotal rotating, idling and positioning functions.
摘要翻译：滑动模块包括滑动构件，该滑动构件具有横向设置并垂直于两个滑动板的大致中间位置并且横向板包括矩形横向槽，并且横向槽包括设置在外部侧的通孔横向槽; 主轴构件是矩形主轴板，并且包括分别设置在所述主轴构件的两侧上的主轴孔，并且心轴螺栓穿过所述主轴孔中的一个并且联接到所述横向槽; 分别包括弹簧钩和弹簧钩之一的拉伸弹簧被锁定在通孔中，另一个弹簧钩被锁定在横向槽上方的主轴螺栓的螺栓孔中; 滑动构件是从动板，其两侧弯曲成滑动槽，用于嵌入滑动板的外侧，并且从动板包括用于使主轴螺栓穿过另一主轴孔并联接主轴螺栓的板孔; 因此，拉伸弹簧如果被按压则存储能量，并且滑动构件在滑动构件被推动超过行进路径的一半以上之后继续滑动到释放能量的位置。滑动模块进一步连接轴结构，轴结构包括垂直的第一枢转轴和水平的第二枢转轴，并且借助于两个枢转轴的安装，滑动模块提供多方向的枢转旋转，空转和定位功能。

2. 发明申请

US20060287164A1 Treadmill roller device having bearing 失效
标题翻译：具有轴承的跑步机滚筒装置
公开(公告)号：US20060287164A1
公开(公告)日：2006-12-21
申请号：US11158709
申请日：2005-06-21
申请人： Chung Chen
发明人： Chung Chen
IPC分类号： A63B22/02
CPC分类号： A63B22/02 , F16C13/022 , F16C35/067 , F16C2316/30
摘要： A roller device for attaching to a shaft of a treadmill, includes a tubular housing having two carriers engaged in the end portions, and the carriers each includes a casing directly folded from the end portion of the housing, and two bearing members are engaged in the casings of the carriers, for engaging with the shaft, and for smoothly and rotatably attaching the housing to the shaft, and for allowing the roller device to be easily and readily attached to treadmills. The casing includes an outer peripheral flap formed integral with the housing, and includes an outer diameter smaller than an inner diameter of the housing, for resiliently supporting the casing within the housing.
摘要翻译：一种用于连接到跑步机的轴的滚子装置，包括一个管状壳体，其具有两个端部，该两个支架接合在该端部中，并且该托架各自包括从该壳体的端部直接折叠的壳体，并且两个轴承部件承载件的壳体，用于与轴接合，并且用于将壳体平滑且可旋转地附接到轴，并且用于允许辊装置容易且容易地附接到跑步机。壳体包括与壳体一体形成的外周翼片，并且包括小于壳体的内径的外径，用于将壳体弹性地支撑在壳体内。

3. 发明申请

US20060207072A1 Rotation-type safety buckle 审中-公开
标题翻译：旋转式安全带扣
公开(公告)号：US20060207072A1
公开(公告)日：2006-09-21
申请号：US11358213
申请日：2006-02-22
申请人： Chung Chen
发明人： Chung Chen
IPC分类号： A44B11/25
CPC分类号： A44B11/2588 , Y10T24/45089 , Y10T24/4522 , Y10T24/45225
摘要： A rotation-type safety buckle comprising of a male fastener and a female fastener is provided. The male fastener has a column at a center of an inner surface thereof, the male fastener has a respective engagement clamper,at each opposite side with respect to the column the engagement clamper is raised from the inner surface of the male fastener such that an opening is provided corresponding to the engagement clamper. The female fastener is provided with a central portion at a center thereof for connecting with the male fastener, the central portion has a wall and defines a guiding hole for receiving the column, and a respective side arm extending from the wall of the central portion is provided to enter the opening of the male fastener for complete engagement with the engagement clamper. The engagement is formed by the male fastener and the female fastener being stacked to each other and connected, making the male fastener rotate clockwise, making the side arm enters the opening of engagement clamper. A secondary protective .engagement function is provided by the protrusion residing within the void of the female fastener after the male fastener rotates clockwise.
摘要翻译：提供了包括阳紧固件和阴紧固件的旋转式安全带扣。阳型紧固件在其内表面的中心具有一个柱，该阳性紧固件具有相应的接合夹持器，在相对于该列的每个相对侧处，接合夹持件从阳型紧固件的内表面升高，使得开口对应于接合夹持器。阴紧固件在其中心处设置有用于与阳紧固件连接的中心部分，中心部分具有壁并且限定用于容纳柱的引导孔，并且从中心部分的壁延伸的相应侧臂是被提供以进入阳紧固件的开口以与接合夹持器完全接合。接合由阳紧固件和阴紧固件彼此堆叠并连接而形成，使得阳性紧固件顺时针旋转，使得侧臂进入接合夹持器的开口。在阳性紧固件顺时针旋转之后，位于阴紧固件的空隙内的突起提供二次保护接触功能。

4. 发明申请

US20050195656A1 Overerase correction in flash EEPROM memory 有权
标题翻译：闪存EEPROM存储器中过度修正
公开(公告)号：US20050195656A1
公开(公告)日：2005-09-08
申请号：US10792121
申请日：2004-03-03
申请人： Chung Chen
发明人： Chung Chen
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/345 , G11C16/3409
摘要： A method of overerase correction for memory cells in a memory array after the memory cells have been erased is provided comprising the following steps: (a) setting a gate voltage of memory cells from a first selected bit line exhibiting leakage current above a threshold value to an initial voltage level; (b) applying a series of overerase correction pulses to the first selected bit line during a selected time period; (c) detecting during the selected time period whether the bit line exhibits leakage current above the threshold value; (d) if the bit line exhibits leakage current above the threshold value after the selected time period, increasing the gate voltage and repeating steps (b) and (c); and (e) if it is detected that the bit line does not exhibit leakage current above the threshold value during the selected time period, selecting a second bit line and repeating steps (a) through (d).
摘要翻译：提供了一种对存储器单元已经被擦除之后的存储器阵列中的存储器单元进行过度修正的方法，包括以下步骤：（a）将表现出高于阈值的泄漏电流的第一选定位线的存储器单元的栅极电压设置为初始电压电平; （b）在所选择的时间周期内对所述第一选定位线施加一系列过度修正脉冲; （c）在所选择的时间段期间检测位线是否表现出高于阈值的漏电流; （d）如果位线在所选择的时间段之后出现高于阈值的泄漏电流，则增加栅极电压并重复步骤（b）和（c）; 以及（e）如果在所选择的时间段内检测到位线没有出现高于阈值的泄漏电流，则选择第二位线并重复步骤（a）至（d）。

5. 发明申请

US20070150907A1 Scheduling method for remote object procedure call and system thereof 审中-公开
标题翻译：远程对象过程调用的调度方法及其系统
公开(公告)号：US20070150907A1
公开(公告)日：2007-06-28
申请号：US11406864
申请日：2006-04-19
申请人： Jenq Lee , Chung Chen , Yu Chang
发明人： Jenq Lee , Chung Chen , Yu Chang
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F9/4881 , G06F9/5038 , G06F2209/484 , G06F2209/5019
摘要： The present invention discloses a scheduling method for remote object procedure call and system thereof, by a two-phase scheduling mechanism to deal with the stateful and stateless invocations simultaneously. First, plural stateful invocations in a workflow are grouped into plural groups of stateful tasks. Then, the groups of stateful tasks are assigned to the server with the minimum load. Next, the rank of each of the stateful and stateless invocations is determined to form a scheduling sequence. An estimated finish time for each stateless invocation for each server is calculated and the stateless invocation is assigned to the server with the minimum estimated finish time.
摘要翻译：本发明公开了一种用于远程对象过程调用的调度方法及其系统，通过两阶段调度机制同时处理有状态和无状态调用。首先，工作流中的多个有状态调用被分组成多组状态任务。然后，将有状态任务组分配给负载最小的服务器。接下来，确定每个有状态和无状态调用的等级以形成调度序列。计算每个服务器的每个无状态调用的估计完成时间，并且将无状态调用分配给具有最小估计完成时间的服务器。

6. 发明授权

US5784377A Integrated digital loop carrier system with virtual tributary mapper circuit 失效
标题翻译：具有虚拟支路映射器电路的集成数字环路载波系统
公开(公告)号：US5784377A
公开(公告)日：1998-07-21
申请号：US471224
申请日：1995-06-06
申请人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
发明人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
IPC分类号： H04J3/16 , H04L12/24 , H04Q3/00 , H04Q11/04 , H04J3/08
CPC分类号： H04L41/0213 , H04J3/1611 , H04L41/0226 , H04L41/046 , H04Q11/0407 , H04Q3/0095 , H04J2203/0028 , H04J2203/0041 , H04J2203/0046 , H04J2203/0048 , H04J2203/006 , H04Q2213/13003 , H04Q2213/1301 , H04Q2213/13106 , H04Q2213/13176 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/13367 , H04Q2213/13381
摘要： An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders and to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the channel units and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier. An application-specific circuit provides such mapping and demapping functions as Floating Byte Synchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Floating Asynchronous VT, DS1 to Locked Byte Synchronous VT, DS1 to Floating Asynchronous VT, and DS1 to Floating Byte Synchronous VT.
摘要翻译：集成数字环路载波（IDLC）系统包括数字线路馈线和信号处理器，与馈线接口并最终向用户设备提供数据。该系统可以用作具有模拟，T1或SONET馈线和任何常规链路介质的中心局终端（COT）或远程数字终端（RDT）。数据采用DS1格式并被复用到光环路上，用于传输到信道单元组，其中光信号被转换为电信号以传送到信道单元和用户。提供了一种用于在集成数字环路载波的RDT中的虚拟支路（VT）和数字信号格式之间映射和解映射信号的方法和装置。应用专用电路提供浮动字节同步VT到锁定字节同步VT，浮动异步VT到锁定字节同步VT，浮动异步VT到浮动异步VT，DS1到锁定字节同步VT，DS1到浮动异步的映射和解映射功能 VT和DS1到浮点字节同步VT。

7. 发明授权

US5608720A Control system and operations system interface for a network element in an access system 失效
标题翻译：访问系统中网元的控制系统和操作系统接口
公开(公告)号：US5608720A
公开(公告)日：1997-03-04
申请号：US258411
申请日：1994-06-10
申请人： Charles H. Biegel , Nicholas J. Carter , Chung Chen , Michael Christofferson , Mahesh P. Desai , Rita A. Eberhart , Steven M. Klonsky , Shaun Missett , Theodore F. Rabenko , John R. Tomassone , David S. Turvene
发明人： Charles H. Biegel , Nicholas J. Carter , Chung Chen , Michael Christofferson , Mahesh P. Desai , Rita A. Eberhart , Steven M. Klonsky , Shaun Missett , Theodore F. Rabenko , John R. Tomassone , David S. Turvene
IPC分类号： H04J3/16 , H04L12/24 , H04Q3/00 , H04Q11/04 , G06F7/00
CPC分类号： H04L41/0213 , H04J3/1611 , H04L41/0226 , H04L41/046 , H04Q11/0407 , H04Q3/0095 , H04J2203/0028 , H04J2203/0041 , H04J2203/0046 , H04J2203/0048 , H04J2203/006 , H04Q2213/13003 , H04Q2213/1301 , H04Q2213/13106 , H04Q2213/13176 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/13367 , H04Q2213/13381
摘要： A control system for a network element (NE) such as a remote digital terminal (RDT) in an integrated digital loop carrier (DLC) system is provided which comprises subsystems for operating circuit packs and for providing functions that are common to the circuit packs. Each subsystem has a subagent residing on a network processor circuit pack. The subagents communicate via a common subagent interface. A NE which supports both OSI and non-OSI interfaces such as Transaction Language 1 (TL1) and Common Management Services Element (CMISE) interfaces is provided, along with a method for mapping TL1 commands to CMISE messages using TL1 proxy objects.
摘要翻译：提供了一种用于诸如综合数字环路载波（DLC）系统中的远程数字终端（RDT）的网元（NE）的控制系统，其包括用于操作电路板的子系统和用于提供电路组共同的功能。每个子系统具有驻留在网络处理器电路板上的子代理。子代理通过通用子代理界面进行通信。提供支持OSI和非OSI接口（例如事务语言1（TL1）和公共管理服务元素（CMISE））接口的网元，以及使用TL1代理对象将TL1命令映射到CMISE消息的方法。

8. 发明申请

US20070155187A1 Method for preparing a gate oxide layer 审中-公开
标题翻译：制备栅极氧化层的方法
公开(公告)号：US20070155187A1
公开(公告)日：2007-07-05
申请号：US11387888
申请日：2006-03-24
申请人： Chung Chen , Chih Chu , Jih Chou
发明人： Chung Chen , Chih Chu , Jih Chou
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/7621 , H01L21/28211 , H01L21/2822 , H01L21/28238 , H01L21/76213
摘要： A method for preparing a gate oxide layer is described. First, a trench surrounding an active area is formed in a substrate, and a dielectric block is then formed in the trench such that an upper surface of the dielectric block is not aligned with that of the substrate. Subsequently, an ion implantation process is performed to implant nitrogen-containing dopants into the substrate in the active area, and a thermal oxidation process is then performed to form a gate oxide layer on the surface of the substrate in the active area. Particularly, the concentration of the nitrogen-containing dopants at the center of the active area is higher than that at the edge of the active area. The nitrogen-containing dopants inhibit the reaction rate of the thermal oxidation process, so as to prevent the gate oxide layer from thinning at the edge near the trench.
摘要翻译：描述了制备栅氧化层的方法。首先，在基板中形成围绕有源区的沟槽，然后在沟槽中形成介质块，使得介质块的上表面与衬底的上表面不一致。随后，进行离子注入工艺以将含氮掺杂剂注入到有源区域中的衬底中，然后执行热氧化工艺以在有源区域中在衬底的表面上形成栅极氧化层。特别地，有源区中心的含氮掺杂剂的浓度高于有源区的边缘处的浓度。含氮掺杂剂抑制热氧化过程的反应速率，以防止栅极氧化层在沟槽附近的边缘变薄。

9. 发明授权

US07079555B2 Integrated digital loop carrier system with virtual tributary mapper circuit 失效
公开(公告)号：US07079555B2
公开(公告)日：2006-07-18
申请号：US09985686
申请日：2001-11-05
申请人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
发明人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
IPC分类号： H04J3/04
CPC分类号： H04L41/0213 , H04J3/1611 , H04J2203/0028 , H04J2203/0041 , H04J2203/0046 , H04J2203/0048 , H04J2203/006 , H04L41/0226 , H04L41/046 , H04Q3/0095 , H04Q11/0407 , H04Q2213/13003 , H04Q2213/1301 , H04Q2213/13106 , H04Q2213/13176 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/13367 , H04Q2213/13381
摘要： An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders an to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the Cus and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier. An application-specific circuit provides such mapping and demapping functions as Floating Byte Synchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Floating Asynchronous VT, DS1 to Locked Byte Synchronous VT, DS1 to Floating Asynchronous VT, and DS1 to Floating Byte Synchronous VT.

10. 发明申请

US20050283336A1 Process independent delay chain 有权
标题翻译：流程独立延迟链
公开(公告)号：US20050283336A1
公开(公告)日：2005-12-22
申请号：US10872018
申请日：2004-06-18
申请人： Chung Chen
发明人： Chung Chen
IPC分类号： G06F19/00 , G11C7/08 , G11C7/22 , H03K5/00 , H03K5/13
CPC分类号： G11C7/08 , G11C7/22 , G11C2207/2254 , H03K5/133 , H03K2005/00123
摘要： An integrated circuit has a circuit for adjusting the time period of an output signal. The adjustment can compensate for semiconductor processing variations varying from wafer to wafer. The circuit adjusts the delay generated by an adjustable delay line, and adjusts the occurrence in time of the trailing edge of the output signal. A value which corresponds with a suitable delay to be generated by the adjustable delay line is stored in nonvolatile storage on the integrated circuit.
摘要翻译：集成电路具有用于调节输出信号的时间周期的电路。该调整可以补偿从晶片到晶片的半导体处理变化。该电路调节由可调延迟线产生的延迟，并调整输出信号后沿时间的出现。与由可调延迟线产生的合适延迟对应的值被存储在集成电路的非易失性存储器中。

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