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1. 发明授权

US5552996A Method and system using the design pattern of IC chips in the processing thereof 失效
标题翻译：在处理IC芯片的设计模式的方法和系统
公开(公告)号：US5552996A
公开(公告)日：1996-09-03
申请号：US390392
申请日：1995-02-16
申请人： Cheryl A. Hoffman , Mark A. Lavin , William Leipold , Kathleen McGroddy , Daniel J. Nickel
发明人： Cheryl A. Hoffman , Mark A. Lavin , William Leipold , Kathleen McGroddy , Daniel J. Nickel
IPC分类号： B24B37/04 , B24B49/00 , H01L21/66 , G06F19/00
CPC分类号： B24B37/005 , B24B37/042 , B24B49/00 , H01L22/20 , Y10S438/941
摘要： The techniques of the present invention facilitate the control of an IC chip fabrication level of a fabrication process based upon the design pattern of the IC chip being fabricated. A grid having multiple sections is imposed over the design pattern of a fabrication level of the IC chip. Then, pattern density values are automatically established for the design pattern contained in each section of the grid. The IC chip fabrication level is then controlled based upon the pattern density values. For example, the established pattern density values facilitate the automatic determination of a CMP process stop parameter, or the automatic compensation for etch rate variations caused by pattern density differences across the design pattern of the IC chip.
摘要翻译：本发明的技术有助于基于正在制造的IC芯片的设计图案来控制制造工艺的IC芯片制造水平。具有多个部分的网格被施加在IC芯片的制造级别的设计图案上。然后，为网格的每个部分中包含的设计模式自动建立模式密度值。然后基于图案密度值来控制IC芯片制造水平。例如，建立的图案密度值有助于自动确定CMP工艺停止参数，或者通过IC芯片的设计图案上的图案密度差导致的蚀刻速率变化的自动补偿。

2. 发明申请

US20060081988A1 Shapes-based migration of aluminum designs to copper damascene 有权
公开(公告)号：US20060081988A1
公开(公告)日：2006-04-20
申请号：US11256025
申请日：2005-10-21
申请人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
发明人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.

3. 发明申请

US20050125756A1 AUTONOMIC GRAPHICAL PARTITIONING 失效
标题翻译：自动图像分割
公开(公告)号：US20050125756A1
公开(公告)日：2005-06-09
申请号：US10707286
申请日：2003-12-03
申请人： Gary Ditlow , Daria Dooling , Timothy Dunham , William Leipold , Stephen Thomas , Ralph Williams
发明人： Gary Ditlow , Daria Dooling , Timothy Dunham , William Leipold , Stephen Thomas , Ralph Williams
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5072
摘要： Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.
摘要翻译：公开了通过基于设计层级中的逻辑宏的大小启发式来识别集成电路设计中的逻辑块来分割集成电路设计的方法和结构。本发明确定逻辑块的数量是否在期望数量的逻辑块的范围内，并重复识别用于集成电路设计的不同层级的逻辑块的处理，直到逻辑块的数量在所需数量的范围内的逻辑块。这作为分配芯片的指南，而不是格栅分割。

4. 发明申请

US20070275551A1 SHAPES-BASED MIGRATION OF ALUMINUM DESIGNS TO COPPER DAMASCENE 失效
公开(公告)号：US20070275551A1
公开(公告)日：2007-11-29
申请号：US11837768
申请日：2007-08-13
申请人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
发明人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
IPC分类号： H01L21/4763
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.

5. 发明申请

US20070211933A1 SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 有权
标题翻译：集成电路系统缺陷的搜索与分析系统
公开(公告)号：US20070211933A1
公开(公告)日：2007-09-13
申请号：US11748575
申请日：2007-05-15
申请人： Bette Reuter , David DeMaris , Mark Lavin , William Leipold , Daniel Maynard , Maharaj Mukherjee
发明人： Bette Reuter , David DeMaris , Mark Lavin , William Leipold , Daniel Maynard , Maharaj Mukherjee
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

6. 发明授权

US07669159B2 IC tiling pattern method, IC so formed and analysis method 有权
标题翻译： IC贴片图案法，IC形成及分析方法
公开(公告)号：US07669159B2
公开(公告)日：2010-02-23
申请号：US11160339
申请日：2005-06-20
申请人： Robert J. Allen , John M. Cohn , Peter A. Habitz , William Leipold , Ivan Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Peter A. Habitz , William Leipold , Ivan Wemple , Paul S. Zuchowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L21/3212 , H01L27/0207
摘要： The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patterns (32, 34) oriented substantially parallel to electrical structure regardless of their angle. A method of electrical analysis based on this provision is also provided as is a related program product.
摘要翻译：本发明提供一种用于提供集成电路（6）的方法，所述集成电路（6）在IC的非正交角的部分（10,12,14和16）之间具有基本均匀的密度。特别地，本发明提供了基本上平行于电气结构定向的填充平铺图案（32,34），而不管其角度如何。还提供了基于该规定的电分析方法，相关程序产品也是如此。

7. 发明申请

US20080104555A1 TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN 有权
标题翻译：测试用于半导体设计的模式敏感算法
公开(公告)号：US20080104555A1
公开(公告)日：2008-05-01
申请号：US11947254
申请日：2007-11-29
申请人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
发明人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36
摘要： A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译：一种用于生成模式敏感算法的测试模式的计算机程序产品。程序产品包括从布局设计中提取特征样本的代码; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。

8. 发明申请

US20070273048A1 SHAPES-BASED MIGRATION OF ALUMINUM DESIGNS TO COPPER DAMASCENE 失效
标题翻译：铝型材的形状移动对铜的吸收
公开(公告)号：US20070273048A1
公开(公告)日：2007-11-29
申请号：US11837723
申请日：2007-08-13
申请人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
发明人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.
摘要翻译：互连结构，制造互连结构的方法以及设计用于半导体器件的互连结构的方法。互连结构包括具有电介质填充孔图案的镶嵌金属线。

9. 发明申请

US20070038970A1 System and method for testing pattern sensitive algorithms for semiconductor design 有权
标题翻译：用于半导体设计测试模式敏感算法的系统和方法
公开(公告)号：US20070038970A1
公开(公告)日：2007-02-15
申请号：US11202591
申请日：2005-08-12
申请人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
发明人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36
摘要： A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译：一种用于生成模式敏感算法的测试模式的系统和方法。该方法包括从布局设计中提取特征样本的步骤; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。

10. 发明申请

US20060023932A1 SYSTEM AND METHOD FOR GENERATING A SET OF TEST PATTERNS FOR AN OPTICAL PROXIMITY CORRECTION ALGORITHM 有权
标题翻译：用于生成一组用于光临近度校正算法的测试模式的系统和方法
公开(公告)号：US20060023932A1
公开(公告)日：2006-02-02
申请号：US10710648
申请日：2004-07-27
申请人： David DeMaris , Mark Lavin , William Leipold , Daniel Maynard , Maharaj Mukherjee
发明人： David DeMaris , Mark Lavin , William Leipold , Daniel Maynard , Maharaj Mukherjee
IPC分类号： G06K9/00 , G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A system and method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.
摘要翻译：一种合成布局图案以测试光学邻近校正算法的系统和方法。该方法包括以下步骤：在一组沃尔什模式矩阵中体现沃尔什模式; 从所述一组沃尔什图案矩阵中处理矩阵组以形成一组测试矩阵; 将测试矩阵的集合映射到测试模式集合。

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