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1. 发明申请

US20070211933A1 SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 有权
标题翻译：集成电路系统缺陷的搜索与分析系统
公开(公告)号：US20070211933A1
公开(公告)日：2007-09-13
申请号：US11748575
申请日：2007-05-15
申请人： Bette Reuter , David DeMaris , Mark Lavin , William Leipold , Daniel Maynard , Maharaj Mukherjee
发明人： Bette Reuter , David DeMaris , Mark Lavin , William Leipold , Daniel Maynard , Maharaj Mukherjee
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

2. 发明申请

US20060023932A1 SYSTEM AND METHOD FOR GENERATING A SET OF TEST PATTERNS FOR AN OPTICAL PROXIMITY CORRECTION ALGORITHM 有权
标题翻译：用于生成一组用于光临近度校正算法的测试模式的系统和方法
公开(公告)号：US20060023932A1
公开(公告)日：2006-02-02
申请号：US10710648
申请日：2004-07-27
申请人： David DeMaris , Mark Lavin , William Leipold , Daniel Maynard , Maharaj Mukherjee
发明人： David DeMaris , Mark Lavin , William Leipold , Daniel Maynard , Maharaj Mukherjee
IPC分类号： G06K9/00 , G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A system and method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.
摘要翻译：一种合成布局图案以测试光学邻近校正算法的系统和方法。该方法包括以下步骤：在一组沃尔什模式矩阵中体现沃尔什模式; 从所述一组沃尔什图案矩阵中处理矩阵组以形成一组测试矩阵; 将测试矩阵的集合映射到测试模式集合。

3. 发明申请

US20050094863A1 SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 有权
标题翻译：集成电路系统缺陷的搜索与分析系统
公开(公告)号：US20050094863A1
公开(公告)日：2005-05-05
申请号：US10605849
申请日：2003-10-30
申请人： Bette Bergman Reuter , David DeMaris , Mark Lavin , William Leipold , Daniel Maynard , Maharaj Mukherjee
发明人： Bette Bergman Reuter , David DeMaris , Mark Lavin , William Leipold , Daniel Maynard , Maharaj Mukherjee
IPC分类号： G06K9/00 , G06T7/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

4. 发明授权

US07669175B2 Methodology to improve turnaround for integrated circuit design using geometrical hierarchy 失效
标题翻译：使用几何层次结构改善集成电路设计周转的方法
公开(公告)号：US07669175B2
公开(公告)日：2010-02-23
申请号：US11747485
申请日：2007-05-11
申请人： James A. Culp , Maharaj Mukherjee , Timothy G. Dunham , Mark Lavin
发明人： James A. Culp , Maharaj Mukherjee , Timothy G. Dunham , Mark Lavin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations on single instance of computational subunits that have an identical geometrical context. Thus, rather than performing such computations based on the functional layout, for which typical design process steps result in significant flattening of the functional hierarchy, and therefore increase the cost of computation, the invention performs simulations on computational subunits stored in a hierarchy based on geometrical context, which minimizes the cost of simulation. The resulting simulation results are subsequently assembled according to the functional layout.
摘要翻译：提供了一种设计用于制造集成电路的布局的方法，其中，通过设计处理的计算密集部分（诸如通过掩模设计传送的图像的模拟）或电路的电特性的模拟被更高效地执行仅在具有相同几何上下文的计算子单元的单个实例上执行这样的计算。因此，不是基于功能布局执行这样的计算，而是通过典型的设计过程步骤导致功能层次结构的显着平坦化，从而增加计算成本，本发明对基于几何的层次结构存储的计算子单元进行模拟上下文，最大限度地降低了模拟成本。随后根据功能布局组合得到的模拟结果。

5. 发明申请

US20050091634A1 Renesting interaction map into design for efficient long range calculations 失效
标题翻译：将交互图重新设计成有效的长距离计算
公开(公告)号：US20050091634A1
公开(公告)日：2005-04-28
申请号：US10694339
申请日：2003-10-27
申请人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
发明人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
IPC分类号： G03F1/08 , G03F1/14 , G03F7/20 , G06F17/50 , H01L21/027 , H01L21/82
CPC分类号： G03F1/36 , G03F1/68 , G06F17/5068
摘要： Methods, and program storage devices, for performing model-based optical lithography corrections by partitioning a cell array layout, having a plurality of polygons thereon, into a plurality of cells covering the layout. This layout is representative of a desired design data hierarchy. A density map is then generated corresponding to interactions between the polygons and plurality of cells, and then the densities within each cell are convolved. An interaction map is formed using the convolved densities, followed by truncating the interaction map to form a map of truncated cells. Substantially identical groupings of the truncated cells are then segregated respectively into differing ones of a plurality of buckets, whereby each of these buckets comprise a single set of identical groupings of truncated cells. A hierarchal arrangement is generated using these buckets, and the desired design data hierarchy enforced using the hierarchal arrangement to ultimately correct for optical lithography.
摘要翻译：方法和程序存储装置，用于通过将具有多个多边形的单元阵列布局划分成覆盖布局的多个单元来执行基于模型的光学光刻校正。该布局代表了所需的设计数据层次结构。然后根据多边形与多个单元之间的相互作用产生密度图，然后卷积每个单元内的密度。使用卷积密度形成交互图，然后截断交互图以形成截断单元格的图。截短的细胞的基本相同的分组然后分别分离成多个桶中的不同的桶，由此这些桶中的每一个都包含一组相同的截断细胞组。使用这些存储桶生成层次排列，并且使用层级排列来强制执行所需的设计数据层级，以最终校正光学光刻。

6. 发明申请

US20070226677A1 PERFORMANCE IN MODEL-BASED OPC ENGINE UTILIZING EFFICIENT POLYGON PINNING METHOD 失效
标题翻译：基于模型的OPC引擎的性能运用有效的聚合方式
公开(公告)号：US20070226677A1
公开(公告)日：2007-09-27
申请号：US11756883
申请日：2007-06-01
申请人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
发明人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Methods, and a program storage device for executing such methods, for performing model-based optical proximity correction by providing a mask matrix having a region of interest (ROI) and locating a plurality of points of interest within the mask matrix. A first polygon having a number of vertices representative of the located points of interest is computed, followed by determining a spatial relation between its vertices and the ROI. The vertices of the first polygon are then pinned to boundaries of and within the ROI such that a second polygon is formed on the ROI. The process is repeated for all vertices of the first polygon such that the second polygon is collapsed onto the ROI. This collapsed second polygon is then used to correct for optical proximity.
摘要翻译：方法和用于执行这种方法的程序存储装置，用于通过提供具有感兴趣区域（ROI）的掩模矩阵并且在掩模矩阵内定位多个感兴趣点来执行基于模型的光学邻近校正。计算具有代表所述定位的兴趣点的顶点数的第一多边形，然后确定其顶点和ROI之间的空间关系。然后将第一多边形的顶点固定在ROI的边界和内部，使得在ROI上形成第二多边形。对第一多边形的所有顶点重复该过程，使得第二多边形折叠到ROI上。然后使用这个折叠的第二个多边形来校正光学接近度。

7. 发明申请

US20050132310A1 Method for optimizing a number of kernels used in a sum of coherent sources for optical proximity correction in an optical microlithography process 有权
标题翻译：用于优化在光学微光刻工艺中用于光学邻近校正的相干光源之和中使用的多个内核的方法
公开(公告)号：US20050132310A1
公开(公告)日：2005-06-16
申请号：US10737626
申请日：2003-12-16
申请人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
发明人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
IPC分类号： G03F1/14 , G06F17/10 , G06F17/50
CPC分类号： G03F1/36
摘要： A method for optimizing the number of kernels N used in a sum of coherent sources (SOCS) for optical proximity correction in an optical microlithography process including setting the number of kernels N to a predetermined minimum value Nmin. A determination is made as to whether an accuracy estimate of calculated intensity is within a tolerable value. A determination is also made as to whether an added X/Y asymmetry estimate of the calculated intensity is negligible.
摘要翻译：一种用于优化在光学微光刻工艺中用于光学邻近校正的相干源（SOCS）之和中使用的内核数N的方法，包括将内核数N设置为预定的最小值Nmin。确定计算强度的精度估计是否在容许值内。还确定所计算的强度的添加的X / Y不对称估计是否可忽略。

8. 发明申请

US20050089211A1 Simultaneous computation of multiple points on one or multiple cut lines 有权
标题翻译：在一条或多条切割线上同时计算多个点
公开(公告)号：US20050089211A1
公开(公告)日：2005-04-28
申请号：US10694299
申请日：2003-10-27
申请人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
发明人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
IPC分类号： H01L21/027 , G03F1/14 , G03F7/20 , G06K9/00 , H01L21/00
CPC分类号： G03F1/36
摘要： Methods, and program storage devices, for performing model-based optical proximity correction by providing a region of interest (ROI) having an interaction distance and locating at least one polygon within the ROI. A cut line of sample points representative of a set of vertices, or plurality of cut lines, are generated within the ROI across at least one lateral edge of the polygon(s). An angular position, and first and second portions of the cut line residing on opposing sides of an intersection between the cut line and the lateral edge of the polygon are determined, followed by generating a new ROI by extending the original ROI beyond its interaction distance based on such angular position, and first and second portions of the cut line. In this manner, a variety of new ROIs may be generated, in a variety of different directions, to ultimately correct for optical proximity.
摘要翻译：方法和程序存储设备，用于通过提供具有交互距离的感兴趣区域（ROI）和定位ROI内的至少一个多边形来执行基于模型的光学邻近度校正。在多边形的至少一个侧边缘上，在ROI内产生代表一组顶点或多个切割线的采样点的切割线。确定角位置，并且切割线的位于切割线和多边形的侧边缘之间的交叉点的相对侧上的切割线的第一和第二部分，然后通过将原始ROI延伸超过其相互作用距离来生成新的ROI 在这种角度位置上，以及切割线的第一和第二部分。以这种方式，可以在各种不同的方向上产生各种新的ROI，以最终校正光学邻近度。

9. 发明申请

US20080037858A1 SIMULTANEOUS COMPUTATION OF MULTIPLE POINTS ON ONE OR MULTIPLE CUT LINES 有权
标题翻译：在多个切割线上同时计算多个点
公开(公告)号：US20080037858A1
公开(公告)日：2008-02-14
申请号：US11874281
申请日：2007-10-18
申请人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
发明人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
IPC分类号： G06K9/00
CPC分类号： G03F1/36
摘要： Methods, and program storage devices, for performing model-based optical proximity correction by providing a region of interest (ROI) having an interaction distance and locating at least one polygon within the ROI. A cut line of sample points representative of a set of vertices, or plurality of cut lines, are generated within the ROI across at least one lateral edge of the polygon(s). An angular position, and first and second portions of the cut line residing on opposing sides of an intersection between the cut line and the lateral edge of the polygon are determined, followed by generating a new ROI by extending the original ROI beyond its interaction distance based on such angular position, and first and second portions of the cut line. In this manner, a variety of new ROIs may be generated, in a variety of different directions, to ultimately correct for optical proximity.
摘要翻译：方法和程序存储设备，用于通过提供具有交互距离的感兴趣区域（ROI）和定位ROI内的至少一个多边形来执行基于模型的光学邻近度校正。在多边形的至少一个侧边缘上，在ROI内产生代表一组顶点或多个切割线的采样点的切割线。确定角位置，并且切割线的位于切割线和多边形的侧边缘之间的交叉点的相对侧上的切割线的第一和第二部分，然后通过将原始ROI延伸超过其相互作用距离来生成新的ROI 在这种角度位置上，以及切割线的第一和第二部分。以这种方式，可以在各种不同的方向上产生各种新的ROI，以最终校正光学邻近度。

10. 发明申请

US20060041851A1 Renesting interaction map into design for efficient long range calculations 有权
公开(公告)号：US20060041851A1
公开(公告)日：2006-02-23
申请号：US11242723
申请日：2005-10-03
申请人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
发明人： Gregg Gallatin , Emanuel Gofman , Kafai Lai , Mark Lavin , Maharaj Mukherjee , Dov Ramm , Alan Rosenbluth , Shlomo Shlafman
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68 , G06F17/5068
摘要： Methods, and program storage devices, for performing model-based optical lithography corrections by partitioning a cell array layout, having a plurality of polygons thereon, into a plurality of cells covering the layout. This layout is representative of a desired design data hierarchy. A density map is then generated corresponding to interactions between the polygons and plurality of cells, and then the densities within each cell are convolved. An interaction map is formed using the convolved densities, followed by truncating the interaction map to form a map of truncated cells. Substantially identical groupings of the truncated cells are then segregated respectively into differing ones of a plurality of buckets, whereby each of these buckets comprise a single set of identical groupings of truncated cells. A hierarchal arrangement is generated using these buckets, and the desired design data hierarchy enforced using the hierarchal arrangement to ultimately correct for optical lithography.

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