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1. 发明申请

US20080104555A1 TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN 有权
标题翻译：测试用于半导体设计的模式敏感算法
公开(公告)号：US20080104555A1
公开(公告)日：2008-05-01
申请号：US11947254
申请日：2007-11-29
申请人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
发明人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36
摘要： A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译：一种用于生成模式敏感算法的测试模式的计算机程序产品。程序产品包括从布局设计中提取特征样本的代码; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。

2. 发明申请

US20070038970A1 System and method for testing pattern sensitive algorithms for semiconductor design 有权
标题翻译：用于半导体设计测试模式敏感算法的系统和方法
公开(公告)号：US20070038970A1
公开(公告)日：2007-02-15
申请号：US11202591
申请日：2005-08-12
申请人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
发明人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36
摘要： A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译：一种用于生成模式敏感算法的测试模式的系统和方法。该方法包括从布局设计中提取特征样本的步骤; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。

3. 发明申请

US20100171031A1 CALIBRATION OF LITHOGRAPHIC PROCESS MODELS 失效
标题翻译：光刻过程模型的校准
公开(公告)号：US20100171031A1
公开(公告)日：2010-07-08
申请号：US12349223
申请日：2009-01-06
申请人： Ioana Graur , Geng Han , Scott M. Mansfield , Michael Scaman
发明人： Ioana Graur , Geng Han , Scott M. Mansfield , Michael Scaman
IPC分类号： G01D18/00
CPC分类号： G03F7/70441 , G03F7/705
摘要： A method is provided for calibrating a model of a lithographic process that includes defining a parameter space of lithographic model parameters that are expected in an integrated circuit layout. The parameter space is defined according to bin values of a lithographic model parameter that span the range from a predetermined minimum and maximum value of the model parameter. The bin values may be incremented uniformly between the maximum and minimum parameter values, or may be distributed according to a weighting. The lithographic model is calibrated to an initial calibration test pattern. The resulting simulated calibration pattern is evaluated to determine whether the model parameter space is adequately populated. If the parameter space is over or under populated, the calibration pattern is modified until the calibration pattern test values adequately populate the parameter space, so that the final calibrated lithographic process model will more reliably predict images over the full range of image parameters.
摘要翻译：提供了一种用于校准光刻工艺的模型的方法，该方法包括定义在集成电路布局中期望的光刻模型参数的参数空间。参数空间根据距离模型参数的预定最小值和最大值的范围的光刻模型参数的二进制值定义。二进制值可以在最大和最小参数值之间均匀递增，也可以根据权重分配。光刻模型被校准为初始校准测试图案。评估所得到的模拟校准模式以确定模型参数空间是否被充分填充。如果参数空间超过或不足，校准模式将被修改，直到校准模式测试值充分填充参数空间，以便最终校准的光刻过程模型将更可靠地在图像参数的全范围内预测图像。

4. 发明授权

US08174681B2 Calibration of lithographic process models 失效
标题翻译：光刻工艺模型的校准
公开(公告)号：US08174681B2
公开(公告)日：2012-05-08
申请号：US12349223
申请日：2009-01-06
申请人： Ioana Graur , Geng Han , Scott M. Mansfield , Michael Scaman
发明人： Ioana Graur , Geng Han , Scott M. Mansfield , Michael Scaman
IPC分类号： G03B27/32 , G01D18/00
CPC分类号： G03F7/70441 , G03F7/705
摘要： A method is provided for calibrating a model of a lithographic process that includes defining a parameter space of lithographic model parameters that are expected in an integrated circuit layout. The parameter space is defined according to bin values of a lithographic model parameter that span the range from a predetermined minimum and maximum value of the model parameter. The bin values may be incremented uniformly between the maximum and minimum parameter values, or may be distributed according to a weighting. The lithographic model is calibrated to an initial calibration test pattern. The resulting simulated calibration pattern is evaluated to determine whether the model parameter space is adequately populated. If the parameter space is over or under populated, the calibration pattern is modified until the calibration pattern test values adequately populate the parameter space, so that the final calibrated lithographic process model will more reliably predict images over the full range of image parameters.
摘要翻译：提供了一种用于校准光刻工艺的模型的方法，该方法包括定义在集成电路布局中期望的光刻模型参数的参数空间。参数空间根据距离模型参数的预定最小值和最大值的范围的光刻模型参数的二进制值定义。二进制值可以在最大和最小参数值之间均匀递增，也可以根据权重分配。光刻模型被校准为初始校准测试图案。评估所得到的模拟校准模式以确定模型参数空间是否被充分填充。如果参数空间超过或不足，校准模式将被修改，直到校准模式测试值充分填充参数空间，以便最终校准的光刻过程模型将在图像参数的全范围内更可靠地预测图像。

5. 发明申请

US20070108984A1 Ionization test for electrical verification 失效
标题翻译：电验证电离试验
公开(公告)号：US20070108984A1
公开(公告)日：2007-05-17
申请号：US10595541
申请日：2003-11-12
申请人： Christopher Cline , Edward Yarmchuk , Vincent Arena , Donald Merte , Thomas Picunko , Brian Wojszynski , Charles Hendricks , Michael Scaman , Robert Olyha , Arnold Halperin
发明人： Christopher Cline , Edward Yarmchuk , Vincent Arena , Donald Merte , Thomas Picunko , Brian Wojszynski , Charles Hendricks , Michael Scaman , Robert Olyha , Arnold Halperin
IPC分类号： G01N27/62
CPC分类号： G01R31/2805 , G01R19/0061 , G01R31/302
摘要： A method and apparatus for the non-contact electrical test of both opens and shorts in electronic substrates. Top surface electrical test features are exposed to an ionization source under ambient conditions and the subsequent charge build up is measured as a drain current by probes contacting corresponding bottom surface features. Opens are detected by an absence of a drain current and shorts are detected by turning off the ionization source and re-measuring the bottom surface probes with a varying bias applied to each probe in the array.
摘要翻译：用于电子基板中的开口和短路的非接触电测试的方法和装置。顶部表面电测试特征在环境条件下暴露于电离源，随后的电荷积聚通过探针接触相应的底表面特征作为漏极电流测量。通过不存在漏极电流来检测开路，并且通过关闭电离源并且利用施加到阵列中的每个探针的变化的偏置来重新测量底表面探针来检测短路。

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