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1. 发明授权

US08470668B2 Method for forming pillar type capacitor of semiconductor device 有权
标题翻译：半导体器件柱状电容器形成方法
公开(公告)号：US08470668B2
公开(公告)日：2013-06-25
申请号：US12979926
申请日：2010-12-28
申请人： Ho Jin Cho , Cheol Hwan Park , Dong Kyun Lee
发明人： Ho Jin Cho , Cheol Hwan Park , Dong Kyun Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10852 , H01L27/10855 , H01L28/90
摘要： An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.
摘要翻译：本发明的实施例包括柱形电容器，其中柱形成在存储节点接触件的上部上。底部电极形成在支柱的侧壁上，电介质膜形成在支柱和底部电极之上。然后在电介质膜的上部上形成顶部电极。

2. 发明授权

US07985645B2 Semiconductor device having a high aspect cylindrical capacitor and method for fabricating the same 有权
标题翻译：具有高方位圆柱形电容器的半导体器件及其制造方法
公开(公告)号：US07985645B2
公开(公告)日：2011-07-26
申请号：US12649610
申请日：2009-12-30
申请人： Cheol Hwan Park , Ho Jin Cho , Dong Kyun Lee
发明人： Cheol Hwan Park , Ho Jin Cho , Dong Kyun Lee
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L27/10894
摘要： A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
摘要翻译：提出了具有高方位圆柱形电容器的半导体器件及其制造方法。高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。存储节点氧化物位于半导体衬底上的周边区域中。导电层涂覆保护环孔。在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。覆盖氧化物部分地填充导电层的一部分。间隙填充膜填充在导电层的其余部分。

3. 发明授权

US07638407B2 Method for forming capacitor of semiconductor device 有权
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US07638407B2
公开(公告)日：2009-12-29
申请号：US12265759
申请日：2008-11-06
申请人： Cheol Hwan Park , Ho Jin Cho , Jae Soo Kim , Dong Kyun Lee
发明人： Cheol Hwan Park , Ho Jin Cho , Jae Soo Kim , Dong Kyun Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/91
摘要： Forming a capacitor of a semiconductor device includes forming an interlayer dielectric having holes over a semiconductor substrate. A conductive layer is then formed on surfaces of the holes and on the upper surface of the interlayer dielectric. A silicon-containing conductive layer is formed by flowing a silicon source gas for the semiconductor substrate formed with the conductive layer, so that silicon atoms can penetrate into the conductive layer. The silicon-containing conductive layer prevents etchant from infiltrating the interlayer dielectric below the silicon-containing conductive layer.
摘要翻译：形成半导体器件的电容器包括在半导体衬底上形成具有孔的层间电介质。然后在孔的表面和层间电介质的上表面上形成导电层。通过使形成有导电层的半导体衬底的硅源气体流动而形成含硅导电层，使得硅原子能够渗透到导电层中。含硅导电层防止蚀刻剂渗透到含硅导电层之下的层间电介质。

4. 发明授权

US07576383B2 Capacitor having tapered cylindrical storage node and method for manufacturing the same 有权
标题翻译：具有锥形圆柱形存储节点的电容器及其制造方法
公开(公告)号：US07576383B2
公开(公告)日：2009-08-18
申请号：US11779093
申请日：2007-07-17
申请人： Ho Jin Cho , Cheol Hwan Park , Jae Soo Kim , Dong Kyun Lee
发明人： Ho Jin Cho , Cheol Hwan Park , Jae Soo Kim , Dong Kyun Lee
IPC分类号： H01L27/108
CPC分类号： H01L28/65 , H01L27/10852 , H01L28/91
摘要： A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.
摘要翻译：通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。在包括孔的模具绝缘层上沉积渐缩层。锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。在存储节点上形成介电层和板状节点。

5. 发明申请

US20120098132A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120098132A1
公开(公告)日：2012-04-26
申请号：US13279546
申请日：2011-10-24
申请人： Cheol Hwan PARK , Ho Jin Cho , Dong Kyun Lee
发明人： Cheol Hwan PARK , Ho Jin Cho , Dong Kyun Lee
IPC分类号： H01L29/43 , H01L21/28
CPC分类号： H01L28/75
摘要： A semiconductor device with a stable structure having high capacitance by changing the pillar type storage node structure and a method of manufacturing the same are provided. The method includes forming a sacrificial layer on a semiconductor substrate including a storage node contact plug, etching the sacrificial layer to form a region exposing the storage node contact plug, forming a first conductive material within an inner side of the region, burying a second conductive material within the region in which the first conductive material is formed, and removing the sacrificial layer to form a pillar type storage node.
摘要翻译：提供了通过改变柱型存储节点结构具有高电容的稳定结构的半导体器件及其制造方法。该方法包括在包括存储节点接触插塞的半导体衬底上形成牺牲层，蚀刻牺牲层以形成露出存储节点接触插塞的区域，在该区域内侧形成第一导电材料，将第二导电在其中形成第一导电材料的区域内的材料，以及去除牺牲层以形成柱状存储节点。

6. 发明授权

US08148764B2 Semiconductor device having a high aspect cylindrical capacitor and method for fabricating the same 有权
标题翻译：具有高方位圆柱形电容器的半导体器件及其制造方法
公开(公告)号：US08148764B2
公开(公告)日：2012-04-03
申请号：US13185873
申请日：2011-07-19
申请人： Cheol Hwan Park , Ho Jin Cho , Dong Kyun Lee
发明人： Cheol Hwan Park , Ho Jin Cho , Dong Kyun Lee
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L27/10894
摘要： A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
摘要翻译：提出了具有高方位圆柱形电容器的半导体器件及其制造方法。高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。存储节点氧化物位于半导体衬底上的周边区域中。导电层涂覆保护环孔。在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。覆盖氧化物部分地填充导电层的一部分。间隙填充膜填充在导电层的其余部分。

7. 发明授权

US07723183B2 Capacitor having tapered cylindrical storage node and method for manufacturing the same 有权
标题翻译：具有锥形圆柱形存储节点的电容器及其制造方法
公开(公告)号：US07723183B2
公开(公告)日：2010-05-25
申请号：US12499248
申请日：2009-07-08
申请人： Ho Jin Cho , Cheol Hwan Park , Jae Soo Kim , Dong Kyun Lee
发明人： Ho Jin Cho , Cheol Hwan Park , Jae Soo Kim , Dong Kyun Lee
IPC分类号： H01L21/02
CPC分类号： H01L28/65 , H01L27/10852 , H01L28/91
摘要： A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.
摘要翻译：通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。在包括孔的模具绝缘层上沉积渐缩层。锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。在存储节点上形成介电层和板状节点。

8. 发明授权

US08476688B2 Semiconductor device and method for manufacturing the same,which prevents leaning of a storage node when forming a capacitor having a plurality of storage nodes of “L” or “+” shape support patterns 失效
标题翻译：半导体装置及其制造方法，当形成具有多个“L”或“+”形状的支撑图案的存储节点的电容器时，防止存储节点倾斜
公开(公告)号：US08476688B2
公开(公告)日：2013-07-02
申请号：US12244115
申请日：2008-10-02
申请人： Ho Jin Cho , Cheol Hwan Park , Jae Wook Seo , Jong Kuk Kim
发明人： Ho Jin Cho , Cheol Hwan Park , Jae Wook Seo , Jong Kuk Kim
IPC分类号： H01L31/113
CPC分类号： H01L28/91 , H01L27/10852
摘要： A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.
摘要翻译：当形成具有高电容的电容器时，防止存储节点倾斜的半导体器件包括形成在半导体衬底上的多个圆柱形存储节点; 以及当从顶部观察时，形成为以“L”或“+”的形式固定存储节点的支撑图案。具有“L”或“+”形式的支撑图案的这种半导体器件随后形成介电层并且防止电容器泄漏的板节点减小了存储节点上的应力。

9. 发明授权

US07906419B2 Laser annealing method for manufacturing semiconductor device 失效
标题翻译：用于制造半导体器件的激光退火方法
公开(公告)号：US07906419B2
公开(公告)日：2011-03-15
申请号：US12275332
申请日：2008-11-21
申请人： Jae Soo Kim , Cheol Hwan Park , Ho Jin Cho
发明人： Jae Soo Kim , Cheol Hwan Park , Ho Jin Cho
IPC分类号： H01L21/3205
CPC分类号： H01L21/268 , H01L27/10876 , H01L29/4236 , H01L29/66621
摘要： A laser annealing method for manufacturing a semiconductor device is presented. The method includes at least two forming steps and one annealing step. The first forming steps includes forming gates on a semiconductor substrate. The second forming step includes forming an insulation layer on the semiconductor substrate and on the gates. The annealing step includes annealing the insulation layer using electromagnetic radiation emitted from a laser.
摘要翻译：提出了一种用于制造半导体器件的激光退火方法。该方法包括至少两个形成步骤和一个退火步骤。第一形成步骤包括在半导体衬底上形成栅极。第二形成步骤包括在半导体衬底上和栅极上形成绝缘层。退火步骤包括使用从激光发射的电磁辐射对绝缘层进行退火。

10. 发明申请

US20080070398A1 Method For Fabricating Semiconductor Device Having Metal Fuse 审中-公开
标题翻译：制造具有金属保险丝的半导体器件的方法
公开(公告)号：US20080070398A1
公开(公告)日：2008-03-20
申请号：US11758512
申请日：2007-06-05
申请人： Dong Su Park , Ho Jin Cho , Keum Bum Lee , Su Jin Chae , Cheol-Hwan Park
发明人： Dong Su Park , Ho Jin Cho , Keum Bum Lee , Su Jin Chae , Cheol-Hwan Park
IPC分类号： H01L23/525
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an antireflection layer containing either silicon or aluminum sequentially from bottom to top on the interlayer insulating layer. The method also includes patterning the antireflection layer, the first metal layer, and the barrier metal layer to form a first metal interconnection. The method also includes forming a fuse with the same material and structure as those of the first metal interconnection while forming the first metal interconnection. The method further includes forming an inter-metal dielectric layer on the first metal interconnection and the fuse, forming a second metal interconnection on the inter-metal dielectric layer, forming a passivation layer on the second metal interconnection, and forming a fuse box in the passivation layer.
摘要翻译：这里公开了一种制造具有金属保险丝的半导体器件的方法。该方法包括在半导体衬底上形成平板电极，在平板电极上形成层间绝缘层，从底部依次形成含有硅或铝的阻挡金属层，第一金属层和含有硅或铝的抗反射层，顶层在层间绝缘层上。该方法还包括图案化抗反射层，第一金属层和阻挡金属层以形成第一金属互连。该方法还包括形成具有与第一金属互连相同的材料和结构的熔丝，同时形成第一金属互连。该方法还包括在第一金属互连和熔丝上形成金属间电介质层，在金属间绝缘层上形成第二金属互连，在第二金属互连上形成钝化层，并在第钝化层。

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