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1. 发明申请

US20070072341A1 Die package and method for making the same 审中-公开
标题翻译：模具包装及其制造方法
公开(公告)号：US20070072341A1
公开(公告)日：2007-03-29
申请号：US11505325
申请日：2006-08-17
申请人： Wei-Chang Tai , Cheng-Yin Lee
发明人： Wei-Chang Tai , Cheng-Yin Lee
IPC分类号： H01L21/78
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/16 , H01L24/48 , H01L25/50 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2225/0651 , H01L2225/06517 , H01L2225/06575 , H01L2225/06582 , H01L2924/00014 , H01L2924/01079 , H01L2924/07811 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a die package and method for making the same. The method of the invention comprises the steps of: (a) providing a plate, having a first surface and a second surface; (b) forming a plurality of first dice on the plate, the first dice having a first surface and a second surface; (c) forming a plurality of bumps on the first surface of the first dice; and (d) cutting the plate to form a plurality of die modules, each module comprising a plate unit, a first die and a plurality of bumps, the first die disposed on a first surface of the plate unit, whereby the bumps could be easily mounted on the single die.
摘要翻译：本发明涉及一种管芯封装及其制造方法。本发明的方法包括以下步骤：（a）提供具有第一表面和第二表面的板; （b）在所述板上形成多个第一骰子，所述第一骰子具有第一表面和第二表面; （c）在第一骰子的第一表面上形成多个凸块; 以及（d）切割所述板以形成多个模具模块，每个模块包括板单元，第一模具和多个凸块，所述第一模具设置在所述板单元的第一表面上，由此所述凸块可以容易地安装在单个模具上。

2. 发明申请

US20050181543A1 SEMICONDUCTOR PACKAGE MODULE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体封装模块及其制造方法
公开(公告)号：US20050181543A1
公开(公告)日：2005-08-18
申请号：US10907561
申请日：2005-04-06
申请人： Shih-Chang Lee , Gwo-Liang Weng , Wei-Chang Tai , Cheng-Yin Lee
发明人： Shih-Chang Lee , Gwo-Liang Weng , Wei-Chang Tai , Cheng-Yin Lee
IPC分类号： H01L23/31 , H01L25/065 , H01L25/10 , H05K1/18 , H05K3/28 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/48
CPC分类号： H01L23/3121 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0655 , H01L2224/05599 , H01L2224/16225 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K1/181 , H05K3/284 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A process for fabricating a multi-chip package module is disclosed. A substrate, at least a first chip and at least a second chip are provided. The backside of the first chip is attached to a die pad on a substrate. A wire-bonding operation is carried out to electrically connect the first chip and the substrate through conductive wires. A plurality of bumps is bonded to the second chip so that one end of each bump is bonded to a contact on the second chip. Thereafter, the other end of each bump is bonded to a contact on the substrate so that the second chip and the substrate are physically and electrically connected together. Finally, an encapsulation process is performed to form a packaging material enclosing the first chip, the second chip, the conductive wires, the bumps and the substrate.
摘要翻译：公开了一种用于制造多芯片封装模块的工艺。提供基板，至少第一芯片和至少第二芯片。第一芯片的背面连接到基板上的芯片焊盘。进行引线接合操作，以通过导线将第一芯片和基板电连接。将多个凸块接合到第二芯片，使得每个凸块的一端接合到第二芯片上的触点。此后，每个凸块的另一端结合到基板上的接触件，使得第二芯片和基板物理和电连接在一起。最后，进行包封处理以形成封装第一芯片，第二芯片，导线，凸块和基板的封装材料。

3. 发明申请

US20070132093A1 SYSTEM-IN-PACKAGE STRUCTURE 有权
标题翻译：系统内包结构
公开(公告)号：US20070132093A1
公开(公告)日：2007-06-14
申请号：US11420230
申请日：2006-05-25
申请人： Meng-Jung Chuang , Cheng-Yin Lee , Wei-Chang Tai , Chi-Chih Chu
发明人： Meng-Jung Chuang , Cheng-Yin Lee , Wei-Chang Tai , Chi-Chih Chu
IPC分类号： H01L23/34
CPC分类号： H01L25/105 , H01L23/3128 , H01L23/49811 , H01L24/48 , H01L24/73 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48471 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K3/284 , H05K3/3452 , H05K2203/0588 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.
摘要翻译：系统级封装结构包括具有成型区域和周边区域的载体基板，至少设置在模制区域中的芯片，覆盖芯片和模制区域的封装，设置在外围区域中的多个焊盘以及设置在周边区域中并部分地暴露焊盘表面的焊接掩模。焊料掩模至少包括其中的空隙。

4. 发明授权

US06815833B2 Flip chip package 有权
公开(公告)号：US06815833B2
公开(公告)日：2004-11-09
申请号：US10657230
申请日：2003-09-09
申请人： Shih-Chang Lee , Gwo-Liang Weng , Wei-Chang Tai , Cheng-Yin Lee
发明人： Shih-Chang Lee , Gwo-Liang Weng , Wei-Chang Tai , Cheng-Yin Lee
IPC分类号： H01L2348
CPC分类号： H01L23/433 , H01L23/3114 , H01L23/4334 , H01L23/49503 , H01L24/48 , H01L2224/05599 , H01L2224/16 , H01L2224/16245 , H01L2224/45099 , H01L2224/48091 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/18161 , H01L2924/3011 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A flip chip package mainly comprises a chip, a leadless lead frame. The leadless lead frame has a die paddle and a plurality of leads. The active surface of the chip has a plurality of bonding pads formed thereon. Besides, a plurality of bumps formed on the bonding pads are electrically connected to the chip, the leads and the die paddle. Therein, the die paddle electrically connected to the chip via the bumps not only prevents the chip from being dislocated but also provides another grounding and heat transmission paths to enhance the electrical, thermal and mechanical performance of the flip chip package. Similarly, the bumps formed on the bonding pads of the chip are electrically connected to the leads so as to fix the chip to the lead frame more securely.

5. 发明授权

US07473629B2 Substrate structure having a solder mask and a process for making the same 有权
标题翻译：具有焊接掩模的基板结构及其制造方法
公开(公告)号：US07473629B2
公开(公告)日：2009-01-06
申请号：US11634059
申请日：2006-12-06
申请人： Wei-Chang Tai , Chi-Chih Chu , Meng-Jung Chuang , Cheng-Yin Lee , Yao-Ting Huang , Kuang-Lin Lo
发明人： Wei-Chang Tai , Chi-Chih Chu , Meng-Jung Chuang , Cheng-Yin Lee , Yao-Ting Huang , Kuang-Lin Lo
IPC分类号： H01L21/44
CPC分类号： H05K3/3452 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H05K3/284 , H05K2203/0588 , H01L2924/00014 , H01L2924/00
摘要： A substrate structure having a solder mask and a process for making the same, including (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. The substrate structure can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.
摘要翻译：一种具有焊料掩模的衬底结构及其制造方法，包括：（a）提供具有顶表面的衬底，所述顶表面具有管芯焊盘和多个焊盘; （b）在所述顶表面上形成第一焊料掩模，所述第一焊料掩模具有多个开口，每个开口对应于每个焊盘，以暴露所述焊盘的至少一部分; 和（c）在第一焊料掩模上形成第二焊料掩模。衬底结构可用于包装较厚的模具，以防止模具裂纹，并避免模塑料的溢流。

6. 发明申请

US20070243704A1 Substrate structure having a solder mask and a process for making the same 有权
标题翻译：具有焊接掩模的基板结构及其制造方法
公开(公告)号：US20070243704A1
公开(公告)日：2007-10-18
申请号：US11634059
申请日：2006-12-06
申请人： Wei-Chang Tai , Chi-Chih Chu , Meng-Jung Chuang , Cheng-Yin Lee , Yao-Ting Huang , Kuang-Lin Lo
发明人： Wei-Chang Tai , Chi-Chih Chu , Meng-Jung Chuang , Cheng-Yin Lee , Yao-Ting Huang , Kuang-Lin Lo
IPC分类号： H01L21/44
CPC分类号： H05K3/3452 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H05K3/284 , H05K2203/0588 , H01L2924/00014 , H01L2924/00
摘要： The present invention relates to a substrate structure having a solder mask and a process for making the same. The process comprises: (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. Whereby, the substrate structure of the invention can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.
摘要翻译：本发明涉及一种具有焊接掩模的基片结构及其制造方法。该方法包括：（a）提供具有顶表面的基底，顶表面具有管芯焊盘和多个焊盘; （b）在所述顶表面上形成第一焊料掩模，所述第一焊料掩模具有多个开口，每个开口对应于每个焊盘，以暴露所述焊盘的至少一部分; 和（c）在第一焊料掩模上形成第二焊料掩模。由此，本发明的基板结构可以用于包装较厚的模具，以防止模具裂纹，并避免模塑料的溢流。

7. 发明申请

US20060110849A1 Method for stacking BGA packages and structure from the same 审中-公开
标题翻译：堆叠BGA封装的方法及其结构
公开(公告)号：US20060110849A1
公开(公告)日：2006-05-25
申请号：US11210700
申请日：2005-08-25
申请人： Cheng-Yin Lee , Wei-Chang Tai
发明人： Cheng-Yin Lee , Wei-Chang Tai
IPC分类号： H01L21/00
CPC分类号： H01L25/50 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H05K3/3436 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： The present invention relates to a method for stacking BGA packages. At first, a first BGA package is provided. The first BGA package includes a first substrate, at least one first chip and a plurality of first connecting balls. The first substrate has a first upper surface and a first bottom surface. The first chip is disposed on the first upper surface. The first connecting balls are disposed on a plurality of first connecting pads of the first upper surface. Then, a second BGA package is provided. The second BGA package includes a second substrate, at least one second chip and a plurality of second connecting balls. The second substrate has a second upper surface and a second bottom surface. The second connecting balls are disposed on a plurality of second connecting pads of the second bottom surface. The second BGA package is stacked on the first BGA package for the second connecting balls to contact the corresponding first connecting balls. Then, the first connecting balls and the corresponding second connecting balls are reflowed into a plurality of integrated spacer balls. The spacer balls connect the first connecting pads and the second connecting pads for providing a stack gap.
摘要翻译：本发明涉及一种用于堆叠BGA封装的方法。首先，提供了第一个BGA封装。第一BGA封装包括第一衬底，至少一个第一芯片和多个第一连接球。第一基板具有第一上表面和第一底表面。第一芯片设置在第一上表面上。第一连接球设置在第一上表面的多个第一连接焊盘上。然后，提供第二个BGA封装。第二BGA封装包括第二衬底，至少一个第二芯片和多个第二连接球。第二基板具有第二上表面和第二底表面。第二连接球设置在第二底面的多个第二连接垫上。第二个BGA封装堆叠在第一个BGA封装上，用于第二个连接球接触相应的第一个连接球。然后，将第一连接球和相应的第二连接球回流到多个集成的间隔球。间隔球连接第一连接焊盘和第二连接焊盘，以提供堆叠间隙。

8. 发明授权

US07417329B2 System-in-package structure 有权
标题翻译：系统级封装结构
公开(公告)号：US07417329B2
公开(公告)日：2008-08-26
申请号：US11420230
申请日：2006-05-25
申请人： Meng-Jung Chuang , Cheng-Yin Lee , Wei-Chang Tai , Chi-Chih Chu
发明人： Meng-Jung Chuang , Cheng-Yin Lee , Wei-Chang Tai , Chi-Chih Chu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/105 , H01L23/3128 , H01L23/49811 , H01L24/48 , H01L24/73 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48471 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K3/284 , H05K3/3452 , H05K2203/0588 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.
摘要翻译：系统级封装结构包括具有成型区域和周边区域的载体基板，至少设置在模制区域中的芯片，覆盖芯片和模制区域的封装，设置在外围区域中的多个焊盘以及设置在周边区域中并部分地暴露焊盘表面的焊接掩模。焊料掩模至少包括其中的空隙。

9. 发明申请

US20050266616A1 Method for balancing molding flow during the assembly of semiconductor packages with defective carrying units 有权
标题翻译：在具有有缺陷的承载单元的半导体封装的组装期间平衡模制流动的方法
公开(公告)号：US20050266616A1
公开(公告)日：2005-12-01
申请号：US11140054
申请日：2005-05-27
申请人： Gwo-Liang Weng , Shih Lee , Wei-Chang Tai
发明人： Gwo-Liang Weng , Shih Lee , Wei-Chang Tai
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/56 , H01L23/16 , H01L23/31 , H01L23/495
CPC分类号： H01L21/561 , H01L21/565 , H01L23/3121 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48237 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01082 , H01L2924/181 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/0665 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for balancing molding flow during the assembly of semiconductor packages with defective carrying units includes providing a chip carrier, which includes a number of good carrying units and at least a defective carrying unit. Then, a number of chips are attached to the good carrying units of the chip carrier, and a chip-imitative glue is formed on the defective carrying unit of the chip carrier. Next, a molding compound is formed on the chip carrier via molding to seal the chips and the chip-imitative glue, thereby improving the balance of molding flow.
摘要翻译：在具有有缺陷的携带单元的半导体封装的组装期间，用于平衡模制流动的方法包括提供包括多个良好的承载单元和至少一个有缺陷的承载单元的芯片载体。然后，将多个芯片附着到芯片载体的良好承载单元，并且在芯片载体的有缺陷的承载单元上形成芯片模拟胶。接下来，通过模制在芯片载体上形成模塑料以密封芯片和芯片模塑胶，从而改善模制流程的平衡。

10. 发明授权

US07195956B2 Method for balancing molding flow during the assembly of semiconductor packages with defective carrying units 有权
标题翻译：在具有有缺陷的承载单元的半导体封装的组装期间平衡模制流动的方法
公开(公告)号：US07195956B2
公开(公告)日：2007-03-27
申请号：US11140054
申请日：2005-05-27
申请人： Gwo-Liang Weng , Shih-Chang Lee , Wei-Chang Tai
发明人： Gwo-Liang Weng , Shih-Chang Lee , Wei-Chang Tai
IPC分类号： H01L21/00
CPC分类号： H01L21/561 , H01L21/565 , H01L23/3121 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48237 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01082 , H01L2924/181 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/0665 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for balancing molding flow during the assembly of semiconductor packages with defective carrying units includes providing a chip carrier, which includes a number of good carrying units and at least a defective carrying unit. Then, a number of chips are attached to the good carrying units of the chip carrier, and a chip-imitative glue is formed on the defective carrying unit of the chip carrier. Next, a molding compound is formed on the chip carrier via molding to seal the chips and the chip-imitative glue, thereby improving the balance of molding flow.
摘要翻译：在具有有缺陷的携带单元的半导体封装的组装期间，用于平衡模制流动的方法包括提供包括多个良好的承载单元和至少一个有缺陷的承载单元的芯片载体。然后，将多个芯片附着到芯片载体的良好承载单元，并且在芯片载体的有缺陷的承载单元上形成芯片模拟胶。接下来，通过模制在芯片载体上形成模塑料以密封芯片和芯片模塑胶，从而改善模制流程的平衡。

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