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1. 发明授权

US06815833B2 Flip chip package 有权
公开(公告)号：US06815833B2
公开(公告)日：2004-11-09
申请号：US10657230
申请日：2003-09-09
申请人： Shih-Chang Lee , Gwo-Liang Weng , Wei-Chang Tai , Cheng-Yin Lee
发明人： Shih-Chang Lee , Gwo-Liang Weng , Wei-Chang Tai , Cheng-Yin Lee
IPC分类号： H01L2348
CPC分类号： H01L23/433 , H01L23/3114 , H01L23/4334 , H01L23/49503 , H01L24/48 , H01L2224/05599 , H01L2224/16 , H01L2224/16245 , H01L2224/45099 , H01L2224/48091 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/18161 , H01L2924/3011 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A flip chip package mainly comprises a chip, a leadless lead frame. The leadless lead frame has a die paddle and a plurality of leads. The active surface of the chip has a plurality of bonding pads formed thereon. Besides, a plurality of bumps formed on the bonding pads are electrically connected to the chip, the leads and the die paddle. Therein, the die paddle electrically connected to the chip via the bumps not only prevents the chip from being dislocated but also provides another grounding and heat transmission paths to enhance the electrical, thermal and mechanical performance of the flip chip package. Similarly, the bumps formed on the bonding pads of the chip are electrically connected to the leads so as to fix the chip to the lead frame more securely.

2. 发明授权

US07195956B2 Method for balancing molding flow during the assembly of semiconductor packages with defective carrying units 有权
标题翻译：在具有有缺陷的承载单元的半导体封装的组装期间平衡模制流动的方法
公开(公告)号：US07195956B2
公开(公告)日：2007-03-27
申请号：US11140054
申请日：2005-05-27
申请人： Gwo-Liang Weng , Shih-Chang Lee , Wei-Chang Tai
发明人： Gwo-Liang Weng , Shih-Chang Lee , Wei-Chang Tai
IPC分类号： H01L21/00
CPC分类号： H01L21/561 , H01L21/565 , H01L23/3121 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48237 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01082 , H01L2924/181 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/0665 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for balancing molding flow during the assembly of semiconductor packages with defective carrying units includes providing a chip carrier, which includes a number of good carrying units and at least a defective carrying unit. Then, a number of chips are attached to the good carrying units of the chip carrier, and a chip-imitative glue is formed on the defective carrying unit of the chip carrier. Next, a molding compound is formed on the chip carrier via molding to seal the chips and the chip-imitative glue, thereby improving the balance of molding flow.
摘要翻译：在具有有缺陷的携带单元的半导体封装的组装期间，用于平衡模制流动的方法包括提供包括多个良好的承载单元和至少一个有缺陷的承载单元的芯片载体。然后，将多个芯片附着到芯片载体的良好承载单元，并且在芯片载体的有缺陷的承载单元上形成芯片模拟胶。接下来，通过模制在芯片载体上形成模塑料以密封芯片和芯片模塑胶，从而改善模制流程的平衡。

3. 发明申请

US20050181543A1 SEMICONDUCTOR PACKAGE MODULE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体封装模块及其制造方法
公开(公告)号：US20050181543A1
公开(公告)日：2005-08-18
申请号：US10907561
申请日：2005-04-06
申请人： Shih-Chang Lee , Gwo-Liang Weng , Wei-Chang Tai , Cheng-Yin Lee
发明人： Shih-Chang Lee , Gwo-Liang Weng , Wei-Chang Tai , Cheng-Yin Lee
IPC分类号： H01L23/31 , H01L25/065 , H01L25/10 , H05K1/18 , H05K3/28 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/48
CPC分类号： H01L23/3121 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0655 , H01L2224/05599 , H01L2224/16225 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K1/181 , H05K3/284 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A process for fabricating a multi-chip package module is disclosed. A substrate, at least a first chip and at least a second chip are provided. The backside of the first chip is attached to a die pad on a substrate. A wire-bonding operation is carried out to electrically connect the first chip and the substrate through conductive wires. A plurality of bumps is bonded to the second chip so that one end of each bump is bonded to a contact on the second chip. Thereafter, the other end of each bump is bonded to a contact on the substrate so that the second chip and the substrate are physically and electrically connected together. Finally, an encapsulation process is performed to form a packaging material enclosing the first chip, the second chip, the conductive wires, the bumps and the substrate.
摘要翻译：公开了一种用于制造多芯片封装模块的工艺。提供基板，至少第一芯片和至少第二芯片。第一芯片的背面连接到基板上的芯片焊盘。进行引线接合操作，以通过导线将第一芯片和基板电连接。将多个凸块接合到第二芯片，使得每个凸块的一端接合到第二芯片上的触点。此后，每个凸块的另一端结合到基板上的接触件，使得第二芯片和基板物理和电连接在一起。最后，进行包封处理以形成封装第一芯片，第二芯片，导线，凸块和基板的封装材料。

4. 发明授权

US07439619B2 Electronic package structure and the packaging process thereof 有权
标题翻译：电子封装结构及其封装过程
公开(公告)号：US07439619B2
公开(公告)日：2008-10-21
申请号：US11028718
申请日：2005-01-03
申请人： Chi-Chih Chu , Gwo-Liang Weng , Shih-Chang Lee
发明人： Chi-Chih Chu , Gwo-Liang Weng , Shih-Chang Lee
IPC分类号： H01L23/34
CPC分类号： H01L23/564 , H01L21/563 , H01L24/83 , H01L24/90 , H01L2224/16 , H01L2224/2929 , H01L2224/293 , H01L2224/83102 , H01L2224/83851 , H01L2224/90 , H01L2224/92125 , H01L2924/14 , H01L2924/1433 , H01L2924/0665 , H01L2924/00014 , H01L2924/00
摘要： The present invention provides an electronic packaging process. The surface of the chip carrier includes at least a chip attachment region and a film attachment region adjacent to the chip attachment region. At least a baffle is formed on the surface of the chip carrier, between the chip attachment region and the film attachment region. After attaching the thin film to the film attachment region of the chip carrier through an affixture layer, the chip is electrically and physically connected to the chip attachment region of the chip carrier through an adhesive layer. The baffle can effectively prevent the gas that is released from the adhesive layer from damaging the bonding between the thin film and the affixture layer. Therefore, almost no bubbles are formed and good electrical connection between the thin film and the affixture layer is maintained.
摘要翻译：本发明提供一种电子包装方法。芯片载体的表面至少包括芯片附着区域和与芯片连接区域相邻的膜附着区域。在芯片载体的表面上，在芯片安装区域和膜附着区域之间形成至少一个挡板。在通过粘合层将薄膜附着到芯片载体的膜附着区域之后，芯片通过粘合剂层电连接并且物理地连接到芯片载体的芯片连接区域。挡板可以有效地防止从粘合剂层释放的气体损害薄膜和固定层之间的粘结。因此，几乎不形成气泡，并且保持薄膜和附着层之间良好的电连接。

5. 发明授权

US07126221B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US07126221B2
公开(公告)日：2006-10-24
申请号：US10868495
申请日：2004-06-14
申请人： Gwo-Liang Weng , Yung-Li Lu , Chi-Chih Chu , Shih-Chang Lee
发明人： Gwo-Liang Weng , Yung-Li Lu , Chi-Chih Chu , Shih-Chang Lee
IPC分类号： H01L23/48 , H01L23/52 , H01L23/40
CPC分类号： H05K3/305 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H05K2201/10734 , H05K2203/0545 , Y02P70/613 , H01L2924/00014
摘要： A semiconductor package comprising a substrate and a semiconductor device disposed on the substrate by flip-chip bonding. The present invention is characterized by a connection structure disposed between the semiconductor device and the substrate that extends along the periphery of the bottom surface of the semiconductor device. As a result, it can preferably provide additional mounting support between the two. The connection structure can be formed from cured adhesive. The present invention also provides a method of manufacturing the semiconductor package.
摘要翻译：一种半导体封装，包括通过倒装芯片接合设置在衬底上的衬底和半导体器件。本发明的特征在于设置在半导体器件和基板之间的连接结构，该连接结构沿着半导体器件的底表面的周边延伸。结果，它可以优选地在两者之间提供附加的安装支撑。连接结构可以由固化的粘合剂形成。本发明还提供一种半导体封装的制造方法。

6. 发明申请

US20050082656A1 Stacked package module 有权
标题翻译：堆叠封装模块
公开(公告)号：US20050082656A1
公开(公告)日：2005-04-21
申请号：US10934409
申请日：2004-09-07
申请人： Chi Chu , Cheng-Yin Lee , Gwo-Liang Weng , Shih-Chang Lee
发明人： Chi Chu , Cheng-Yin Lee , Gwo-Liang Weng , Shih-Chang Lee
IPC分类号： H01L25/065 , H01L23/02
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2224/81193 , H01L2225/06513 , H01L2225/06527 , H01L2225/06551 , H01L2924/01079 , H01L2924/01322 , H01L2924/15311 , H01L2924/18161
摘要： A Stackable package module comprises a plurality of semiconductor devices in stack. One of the semiconductor devices includes a chip with an active surface and a corresponding back surface, a plurality of solder bumps and a plurality of stud bumps. The solder bumps are formed on the active surface. The stud bumps are formed on the back surface. Each stud bump has a bump body and a protruding trail by wire-bonding and cutting. Bumps of another package are bonded on the stub bumps for replacing known intermediate substrate in conventional stacked package module.
摘要翻译：可堆叠封装模块包括堆叠中的多个半导体器件。半导体器件中的一个包括具有活性表面和对应的背面的芯片，多个焊料凸块和多个凸块凸块。焊料凸块形成在有源表面上。柱形凸块形成在背面。每个柱形凸起具有凸起体和通过引线接合和切割的突出轨迹。另一个封装的凸块被结合在短截线凸起上，用于替代传统堆叠封装模块中的已知中间衬底。

7. 发明授权

US07187070B2 Stacked package module 有权
标题翻译：堆叠封装模块
公开(公告)号：US07187070B2
公开(公告)日：2007-03-06
申请号：US10934409
申请日：2004-09-07
申请人： Chi Chih Chu , Cheng-Yin Lee , Gwo-Liang Weng , Shih-Chang Lee
发明人： Chi Chih Chu , Cheng-Yin Lee , Gwo-Liang Weng , Shih-Chang Lee
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2224/81193 , H01L2225/06513 , H01L2225/06527 , H01L2225/06551 , H01L2924/01079 , H01L2924/01322 , H01L2924/15311 , H01L2924/18161
摘要： A Stackable package module comprises a plurality of semiconductor devices in stack. One of the semiconductor devices includes a chip with an active surface and a corresponding back surface, a plurality of solder bumps and a plurality of stud bumps. The solder bumps are formed on the active surface. The stud bumps are formed on the back surface. Each stud bump has a bump body and a protruding trail by wire-bonding and cutting. Bumps of another package are bonded on the stub bumps for replacing known intermediate substrate in conventional stacked package module.
摘要翻译：可堆叠封装模块包括堆叠中的多个半导体器件。半导体器件中的一个包括具有活性表面和对应的背面的芯片，多个焊料凸块和多个凸块凸块。焊料凸块形成在有源表面上。柱形凸块形成在背面。每个柱形凸起具有凸起体和通过引线接合和切割的突出轨迹。另一个封装的凸块被结合在短截线凸起上，用于替代传统堆叠封装模块中的已知中间衬底。

8. 发明申请

US20050168906A1 Contact sensor package 有权
标题翻译：接触传感器包装
公开(公告)号：US20050168906A1
公开(公告)日：2005-08-04
申请号：US11044027
申请日：2005-01-28
申请人： Gwo-Liang Weng , Che-Ya Chou , Shih-Chang Lee
发明人： Gwo-Liang Weng , Che-Ya Chou , Shih-Chang Lee
IPC分类号： G06K9/00 , H01L23/28 , H02H1/04
CPC分类号： G06K9/00053 , H01L2224/48091 , H01L2224/48227 , H01L2224/8592 , H01L2924/00014
摘要： A contact sensor chip package includes a substrate, a contact sensor chip, a ground member and an encapsulation. The contact sensor chip is disposed on the substrate, and the contact sensor chip has a sensor area. The ground member is disposed on the ground pad of the substrate, and the ground member is electrically connected to the ground pad. The encapsulation covers the contact sensor chip and the ground member, wherein the sensor area of the contact sensor chip and a portion of the ground member are exposed out of the encapsulation.
摘要翻译：接触传感器芯片封装包括基板，接触传感器芯片，接地部件和封装。接触传感器芯片设置在基板上，并且接触传感器芯片具有传感器区域。接地部件设置在基板的接地焊盘上，并且接地部件电连接到接地焊盘。封装覆盖接触传感器芯片和接地部件，其中接触传感器芯片的传感器区域和接地部件的一部分暴露在封装之外。

9. 发明授权

US06257857B1 Molding apparatus for flexible substrate based package 有权
标题翻译：用于基于柔性基板的包装的成型装置
公开(公告)号：US06257857B1
公开(公告)日：2001-07-10
申请号：US09494649
申请日：2000-01-31
申请人： Shih-Chang Lee , Gwo Liang Weng
发明人： Shih-Chang Lee , Gwo Liang Weng
IPC分类号： B29C4514
CPC分类号： B29C45/14655 , H01L21/565 , H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2924/181 , Y10T428/234 , Y10T428/24612 , H01L2924/00014 , H01L2924/00012
摘要： A molding apparatus for use in forming a flexible substrate based package comprises a plurality of pots. Two flexible substrates are installed at two sides of the pots. A plurality of sets of chips mounted on the upper surface of the substrate wherein each set of chips is in an array arrangement. The molding apparatus further comprises a plurality of runners. Each runner independently extends from one side of the pot to one side of the substrate, and connects to a cavity of a upper part of a mold disposed on the substrate through a gate. The present invention characterized in that, the molding apparatus is provided with a first communication channel formed corresponding to one side of the substrate and a second communication channel formed corresponding to the other side of the substrate. The first and the second communication channels interconnect the cavities at two opposite sides thereof. Therefore, the molded product removed from the mold has a first and a second connection bar, which form interconnection at two opposite sides of each unit package body thereby integrating all unit package bodies, and thereby enhancing the mechanical strength of the molded product.
摘要翻译：用于形成基于柔性基底的包装的成型装置包括多个盆。两个柔性基板安装在锅的两侧。安装在基板的上表面上的多组芯片，其中每组芯片是阵列布置。成型装置还包括多个流道。每个流道独立地从罐的一侧延伸到基板的一侧，并且通过浇口连接到设置在基板上的模具的上部的空腔。本发明的特征在于，所述成型装置设置有与所述基板的一侧对应地形成的第一连通流路和与所述基板的另一侧对应地形成的第二连通流路。第一和第二通信通道将空腔的两个相对侧互连。因此，从模具中取出的模制产品具有第一和第二连接杆，其在每个单元封装主体的两个相对侧形成互连，从而整合所有单元封装主体，从而增强模制产品的机械强度。

10. 发明授权

US07193282B2 Contact sensor package 有权
标题翻译：接触传感器包装
公开(公告)号：US07193282B2
公开(公告)日：2007-03-20
申请号：US11044027
申请日：2005-01-28
申请人： Gwo-Liang Weng , Che-Ya Chou , Shih-Chang Lee
发明人： Gwo-Liang Weng , Che-Ya Chou , Shih-Chang Lee
IPC分类号： H01L27/14
CPC分类号： G06K9/00053 , H01L2224/48091 , H01L2224/48227 , H01L2224/8592 , H01L2924/00014
摘要： A contact sensor chip package includes a substrate, a contact sensor chip, a ground member and an encapsulation. The contact sensor chip is disposed on the substrate, and the contact sensor chip has a sensor area. The ground member is disposed on the ground pad of the substrate, and the ground member is electrically connected to the ground pad. The encapsulation covers the contact sensor chip and the ground member, wherein the sensor area of the contact sensor chip and a portion of the ground member are exposed out of the encapsulation.
摘要翻译：接触传感器芯片封装包括基板，接触传感器芯片，接地部件和封装。接触传感器芯片设置在基板上，并且接触传感器芯片具有传感器区域。接地部件设置在基板的接地焊盘上，并且接地部件电连接到接地焊盘。封装覆盖接触传感器芯片和接地部件，其中接触传感器芯片的传感器区域和接地部件的一部分暴露在封装之外。

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