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    • 1. 发明授权
    • Memory test system for peak power reduction
    • 用于峰值功率降低的内存测试系统
    • US06978411B2
    • 2005-12-20
    • US10265700
    • 2002-10-08
    • Cheng-I HuangChen-Teng FanWang-Jin ChenJyh-Herny Wang
    • Cheng-I HuangChen-Teng FanWang-Jin ChenJyh-Herny Wang
    • G11C29/56G01R31/28
    • G11C29/56012G11C29/56
    • A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.
    • 用于峰值功率降低的记忆测试系统。 存储器测试系统包括多个存储器,多个存储器内置自检电路和多个延迟单元。 每个存储器内置的自检电路包括内置的自检控制器,用于接收时钟信号并产生多个所需的控制信号以测试其中一个存储器。 每个延迟单元耦合在两个相邻的内置自检控制器之间。 输入到内置自检控制器之一的时钟信号由延迟单元接收以产生延迟的时钟信号,并且延迟单元将延迟的时钟信号输出到另一个。
    • 4. 发明授权
    • Mux scan cell with delay circuit for reducing hold-time violations
    • 具有延迟电路的Mux扫描单元,以减少持续时间违规
    • US06895540B2
    • 2005-05-17
    • US10064475
    • 2002-07-18
    • Wang-Jin ChenChen-Teng FanCheng-I Huang
    • Wang-Jin ChenChen-Teng FanCheng-I Huang
    • G01R31/3185G01R31/28G06F9/45H01L25/00
    • G01R31/318594G01R31/318541
    • A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.
    • 多路复用扫描单元包括多路复用器,其具有用于接收原始数据的第一输入节点,用于接收测试数据的第二输入节点,输出节点,选择节点和电连接在第二输入节点和输出节点之间的延迟电路,用于 延长测试数据从第二输入节点到输出节点行进的行进时间。 复用器扫描单元还包括连接到多路复用器的触发器。 利用延迟电路,延长测试数据的行进时间,使得测试数据从第二输入节点行进到输出节点的行进时间模拟原始数据行进通过的行进时间的总和 组合逻辑和原始数据从第一输入节点传播到输出节点的行进时间。
    • 7. 发明授权
    • Built-in self test for system in package
    • 内置自检系统的包装
    • US07394272B2
    • 2008-07-01
    • US11306773
    • 2006-01-11
    • Wang-Jin ChenAviles Chang
    • Wang-Jin ChenAviles Chang
    • G01R31/02
    • G01R31/31855G11C5/04G11C29/36G11C2029/0405G11C2029/3602
    • A SIP (system in package) with a chip and a memory mode, capable of performing integration test on the memory module even if the memory module does not include any scan chain is provided. The chip has a built-in self-test (BIST) circuit, which generates test pattern signals to test the memory module in response to a mode signal. Under a test mode, after the memory module receives the test pattern signals, the memory module outputs responsive readout signals to the BIST circuit and the BIST circuit determines and outputs a test result and a test record in response to the readout signals. If the test fails, conditions of the faulty memory module are recognized from the test record.
    • 提供具有芯片和存储器模式的SIP(包括系统),能够对存储器模块执行集成测试,即使存储器模块不包括任何扫描链。 该芯片具有内置自检(BIST)电路,可生成测试模式信号,以响应模式信号测试存储器模块。 在测试模式下,在存储器模块接收测试模式信号之后,存储器模块向BIST电路输出响应读出信号,并且BIST电路响应于读出信号确定并输出测试结果和测试记录。 如果测试失败,则从测试记录中识别故障存储器模块的状况。
    • 8. 发明申请
    • BUILT-IN SELF TEST FOR SYSTEM IN PACKAGE
    • 内置系统自检测试
    • US20070159201A1
    • 2007-07-12
    • US11306773
    • 2006-01-11
    • Wang-Jin ChenAviles Chang
    • Wang-Jin ChenAviles Chang
    • G01R31/26
    • G01R31/31855G11C5/04G11C29/36G11C2029/0405G11C2029/3602
    • A SIP (system in package) with a chip and a memory mode, capable of performing integration test on the memory module even if the memory module does not include any scan chain is provided. The chip has a built-in self-test (BIST) circuit, which generates test pattern signals to test the memory module in response to a mode signal. Under a test mode, after the memory module receives the test pattern signals, the memory module outputs responsive readout signals to the BIST circuit and the BIST circuit determines and outputs a test result and a test record in response to the readout signals. If the test fails, conditions of the faulty memory module are recognized from the test record.
    • 提供具有芯片和存储器模式的SIP(包括系统),能够对存储器模块执行集成测试,即使存储器模块不包括任何扫描链。 该芯片具有内置自检(BIST)电路,可生成测试模式信号,以响应模式信号测试存储器模块。 在测试模式下,在存储器模块接收测试模式信号之后,存储器模块向BIST电路输出响应读出信号,并且BIST电路响应于读出信号确定并输出测试结果和测试记录。 如果测试失败,则从测试记录中识别故障存储器模块的状况。