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1. 发明申请

US20060197518A1 PARAMETRIC MEASURING CIRCUIT FOR MINIMIZING OSCILLATION EFFECT 审中-公开
公开(公告)号：US20060197518A1
公开(公告)日：2006-09-07
申请号：US11306382
申请日：2005-12-27
申请人： Shyh-An Chi , Wang-Jin Chen
发明人： Shyh-An Chi , Wang-Jin Chen
IPC分类号： G01R31/28
CPC分类号： G01R31/31712
摘要： A parametric measuring circuit for minimizing an oscillation effect is provided. The parametric measuring circuit comprises an input detection circuit, an oscillation effect eliminating logic circuit and an output selection circuit. The input detection circuit receives an input signal from an external input terminal and outputs the detection signal. The oscillation effect eliminating logic circuit is coupled to the input detection circuit for reducing/eliminating oscillation effect and outputting the detection signal. The output selection circuit is coupled to the oscillation effect eliminating logic circuit to select and transmit either the output signal generated from the internal circuit or the detection signal to the output terminal.

2. 发明授权

US08716855B2 Integrated circuit system with distributed power supply comprising interposer and voltage regulator module 有权
标题翻译：具有分布式电源的集成电路系统，包括插入器和电压调节器模块
公开(公告)号：US08716855B2
公开(公告)日：2014-05-06
申请号：US12943395
申请日：2010-11-10
申请人： Shyh-An Chi , Mark Shane Peng , Yun-Han Lee
发明人： Shyh-An Chi , Mark Shane Peng , Yun-Han Lee
IPC分类号： H01L23/52
CPC分类号： H01L23/49811 , H01L23/481 , H01L23/49816 , H01L23/50 , H01L24/48 , H01L24/73 , H01L25/18 , H01L2224/06181 , H01L2224/13025 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01033 , H01L2924/14 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads.
摘要翻译：一种具有插入器和具有第一和第二接合焊盘的集成电路的集成电路系统，所述集成电路管芯使用所述第一接合焊盘接合到所述插入器。具有在不同工作电压下操作的电路块的集成电路和与集成电路的第二接合焊盘键合的电压调节器模块。电压调节器模块将电源电压转换为相应电路块的工作电压，并通过第二接合焊盘将相应的工作电压提供给电路块。

3. 发明授权

US08547151B2 Phase-locked loops that share a loop filter 有权
标题翻译：共享环路滤波器的锁相环路
公开(公告)号：US08547151B2
公开(公告)日：2013-10-01
申请号：US13407394
申请日：2012-02-28
申请人： Feng Wei Kuo , Shyh-An Chi , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
发明人： Feng Wei Kuo , Shyh-An Chi , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/06 , H03L7/093 , H03L7/099
摘要： A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits.
摘要翻译：集成电路的管芯堆叠包括多个管芯。芯片堆叠中的每个裸片包括锁相环（PLL）。每个模具中的PLL共享一个环路滤波器和其他相应的电路。

4. 发明授权

US08803581B2 Fast flip-flop structure with reduced set-up time 有权
标题翻译：快速的触发器结构，缩短设置时间
公开(公告)号：US08803581B2
公开(公告)日：2014-08-12
申请号：US12758451
申请日：2010-04-12
申请人： Shyh-An Chi , Shiue Tsong Shen , Jeff Lee , Frank Y. Lee
发明人： Shyh-An Chi , Shiue Tsong Shen , Jeff Lee , Frank Y. Lee
IPC分类号： H03K3/289 , H03K3/012
CPC分类号： H03K3/012 , G01R31/318541
摘要： A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.
摘要翻译：提供了一种具有缩短设置时间的触发器结构。触发器包括通过由时钟信号控制的第一开关接收功能数据的第一主锁存器，第二主锁存器通过由时钟信号控制的第二开关接收扫描数据，以及从锁存器连接到第一主器件通过由时钟信号控制的第三开关锁存。第二主锁存器通过由扫描使能信号控制的第四开关耦合到第一主锁存器，使得扫描使能信号控制功能数据或扫描数据是否变为从第一主锁存器到从锁存器的输出，以及从锁存器用于锁存和传输来自第一主锁存器的输出。

5. 发明授权

US08719463B2 Processor with tightly coupled smart memory unit 有权
标题翻译：具有紧耦合智能存储单元的处理器
公开(公告)号：US08719463B2
公开(公告)日：2014-05-06
申请号：US12947177
申请日：2010-11-16
申请人： Shyh-An Chi
发明人： Shyh-An Chi
IPC分类号： G06F13/28 , G06F13/40
CPC分类号： G06F13/28 , G06F12/1081 , G06F13/24 , G06F13/32 , G06F13/4063 , G06F15/7821 , G06F2212/2532 , Y02D10/14 , Y02D10/151
摘要： An information processor includes a central processing unit core and a tightly coupled smart memory unit, the central processing unit core having a direct memory access unit. The tightly coupled smart memory unit having a memory unit coupled to the central processing unit core and a control register, and status register coupled to the central processing unit core and a local processing unit that processes data stored in the memory unit.
摘要翻译：信息处理器包括中央处理单元核心和紧密耦合的智能存储器单元，所述中央处理单元核心具有直接存储器存取单元。紧耦合的智能存储器单元具有耦合到中央处理单元核心的存储单元和控制寄存器，以及耦合到中央处理单元核心的状态寄存器和处理存储在存储器单元中的数据的本地处理单元。

6. 发明申请

US20080136400A1 Dynamic voltage and frequency management in integrated circuits 有权
公开(公告)号：US20080136400A1
公开(公告)日：2008-06-12
申请号：US11636171
申请日：2006-12-07
申请人： Shyh-An Chi , Chih-Hung Chung
发明人： Shyh-An Chi , Chih-Hung Chung
IPC分类号： G06F1/26 , H03K3/03 , H03L7/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of continuous pulses with frequencies reflecting the process parameter, operating voltage and temperature effects in the IC, a period generator for generating at least one gating period with a predetermined duration, a plurality of counters coupling to the plurality of ring oscillators as well as the period generator for counting the number of the continuous pulses in the gating period, at least one selector for selecting a predetermined number counted by the plurality of counters, and at least one voltage-and-frequency adjustment circuitry for adjusting one or more operating voltages or one or more clock frequencies in the IC based on the predetermined number selected by the selector, wherein the IC operating voltage or clock frequency correlates with the ring oscillator frequencies.

7. 发明授权

US09412708B2 Enhanced ESD protection of integrated circuit in 3DIC package 有权
标题翻译： 3DIC封装中集成电路的增强ESD保护
公开(公告)号：US09412708B2
公开(公告)日：2016-08-09
申请号：US13009612
申请日：2011-01-19
申请人： Shyh-An Chi
发明人： Shyh-An Chi
IPC分类号： H02H9/00 , H01L23/60 , H01L25/065 , H01L23/498 , H01L23/50
CPC分类号： H01L23/60 , H01L23/49822 , H01L23/50 , H01L25/0655 , H01L25/0657 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2924/15192 , H01L2924/15311
摘要： Enhanced electrostatic discharge (ESD) protection schemes of an integrated circuit in three-dimensional (3D) integrated circuit (ICs) packages, and methods of forming the same are presented in the disclosure. An array of ESD protection devices can be formed in an interposer and placed under one or a plurality of ICs so that a hard block inside an IC on top of the interposer can be connected to an ESD protection device of the array and is protected from ESD. The ESD protection device cell of the array is connected to a Voltage Regulator Module (VRM) which can be placed inside the interposer, on the surface of the interposer, or on the surface of a printed circuit board (PCB). The ESD protection array is of generic nature and can be used with many kinds of ICs to form a three-dimensional IC package. Further embodiments of ESD protection for 3D IC package is disclosed where an ESD protection device inside a first IC 2 can be shared with another IC 1 to protect a hard block within IC 1.
摘要翻译：本发明公开了三维（3D）集成电路（IC）封装中集成电路的增强型静电放电（ESD）保护方案及其形成方法。 ESD保护器件的阵列可以形成在插入器中并放置在一个或多个IC下方，使得内插器顶部的IC内部的硬块可以连接到阵列的ESD保护器件并且被保护免受ESD 。该阵列的ESD保护器件单元连接到一个稳压器模块（VRM），可以放置在插入器内部，插入表面或印刷电路板（PCB）表面上。 ESD保护阵列具有通用性，可与多种IC一起使用，形成三维IC封装。公开了用于3D IC封装的ESD保护的其它实施例，其中第一IC 2内部的ESD保护装置可以与另一IC 1共享以保护IC 1内的硬块。

8. 发明授权

US09064715B2 Networking packages based on interposers 有权
标题翻译：基于插件的网络包
公开(公告)号：US09064715B2
公开(公告)日：2015-06-23
申请号：US12964503
申请日：2010-12-09
申请人： Yun-Han Lee , Mark Shane Peng , Shyh-An Chi
发明人： Yun-Han Lee , Mark Shane Peng , Shyh-An Chi
IPC分类号： H05K1/11 , H05K1/14 , H01L25/065 , H01L25/18 , H01L23/00 , H01L23/14 , H01L23/538
CPC分类号： H05K1/181 , H01L23/147 , H01L23/538 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2223/6677 , H01L2224/16225 , H01L2224/16235 , H01L2225/06565 , H01L2924/14 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1438 , H01L2924/15192 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H05K1/111 , H05K1/115 , H05K1/141 , H05K2201/10045 , H05K2201/10053 , H05K2201/10378 , H01L2924/00
摘要： A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.
摘要翻译：一种包装结构包括一个包括多个交换机/路由器的联网单元和耦合到该多个交换机/路由器的多个网络接口单元，以及包括多个金属连接的插件。内插器基本上没有内置的功能元件。功能元件在插入器之外并且结合到插入器上，其中功能元件通过多个金属连接电耦合到联网单元。

9. 发明授权

US08552795B2 Substrate bias control circuit for system on chip 有权
标题翻译：衬底系统片上偏置控制电路
公开(公告)号：US08552795B2
公开(公告)日：2013-10-08
申请号：US12793884
申请日：2010-06-04
申请人： Shyh-An Chi , Shiue Tsong Shen , Jyy Anne Lee , Yun-Han Lee
发明人： Shyh-An Chi , Shiue Tsong Shen , Jyy Anne Lee , Yun-Han Lee
IPC分类号： G05F3/08 , H03K17/14
CPC分类号： G05F3/205 , H03K19/00384
摘要： A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.
摘要翻译：衬底偏置控制电路包括响应PVT效应的工艺电压温度（PVT）效应传感器。 PVT效应量化器耦合到PVT效应传感器。 PVT效应量词量化PVT效应以提供输出。 PVT效应量化器包括至少一个计数器和周期发生器。周期发生器为计数器提供一个时间段。耦合到PVT效应量化器的偏置控制器被配置为接收PVT效应量化器的输出。偏置控制器被配置为提供偏置电压。偏置控制器包括偏置电压比较器。

10. 发明申请

US20120182650A1 Enhanced ESD Protection of Integrated Circuit in 3DIC package 有权
标题翻译： 3DIC封装中集成电路的增强ESD保护
公开(公告)号：US20120182650A1
公开(公告)日：2012-07-19
申请号：US13009612
申请日：2011-01-19
申请人： Shyh-An Chi
发明人： Shyh-An Chi
IPC分类号： H02H9/00 , H01L21/50
CPC分类号： H01L23/60 , H01L23/49822 , H01L23/50 , H01L25/0655 , H01L25/0657 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2924/15192 , H01L2924/15311
摘要： Enhanced electrostatic discharge (ESD) protection schemes of an integrated circuit in three-dimensional (3D) integrated circuit (ICs) packages, and methods of forming the same are presented in the disclosure. An array of ESD protection devices can be formed in an interposer and placed under one or a plurality of ICs so that a hard block inside an IC on top of the interposer can be connected to an ESD protection device of the array and is protected from ESD. The ESD protection device cell of the array is connected to a Voltage Regulator Module (VRM) which can be placed inside the interposer, on the surface of the interposer, or on the surface of a printed circuit board (PCB). The ESD protection array is of generic nature and can be used with many kinds of ICs to form a three-dimensional IC package. Further embodiments of ESD protection for 3D IC package is disclosed where an ESD protection device inside a first IC 2 can be shared with another IC 1 to protect a hard block within IC 1.
摘要翻译：本发明公开了三维（3D）集成电路（IC）封装中集成电路的增强型静电放电（ESD）保护方案及其形成方法。 ESD保护器件的阵列可以形成在插入器中并放置在一个或多个IC下方，使得内插器顶部的IC内部的硬块可以连接到阵列的ESD保护器件并且被保护免受ESD 。该阵列的ESD保护器件单元连接到一个稳压器模块（VRM），可以放置在插入器内部，插入表面或印刷电路板（PCB）表面上。 ESD保护阵列具有通用性，可与多种IC一起使用，形成三维IC封装。公开了用于3D IC封装的ESD保护的其它实施例，其中第一IC 2内部的ESD保护装置可以与另一IC 1共享以保护IC 1内的硬块。

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