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    • 4. 发明授权
    • Fast flip-flop structure with reduced set-up time
    • 快速的触发器结构,缩短设置时间
    • US08803581B2
    • 2014-08-12
    • US12758451
    • 2010-04-12
    • Shyh-An ChiShiue Tsong ShenJeff LeeFrank Y. Lee
    • Shyh-An ChiShiue Tsong ShenJeff LeeFrank Y. Lee
    • H03K3/289H03K3/012
    • H03K3/012G01R31/318541
    • A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.
    • 提供了一种具有缩短设置时间的触发器结构。 触发器包括通过由时钟信号控制的第一开关接收功能数据的第一主锁存器,第二主锁存器通过由时钟信号控制的第二开关接收扫描数据,以及从锁存器连接到第一主器件 通过由时钟信号控制的第三开关锁存。 第二主锁存器通过由扫描使能信号控制的第四开关耦合到第一主锁存器,使得扫描使能信号控制功能数据或扫描数据是否变为从第一主锁存器到从锁存器的输出,以及 从锁存器用于锁存和传输来自第一主锁存器的输出。
    • 7. 发明授权
    • Enhanced ESD protection of integrated circuit in 3DIC package
    • 3DIC封装中集成电路的增强ESD保护
    • US09412708B2
    • 2016-08-09
    • US13009612
    • 2011-01-19
    • Shyh-An Chi
    • Shyh-An Chi
    • H02H9/00H01L23/60H01L25/065H01L23/498H01L23/50
    • H01L23/60H01L23/49822H01L23/50H01L25/0655H01L25/0657H01L2224/14181H01L2224/16145H01L2224/16225H01L2224/1703H01L2224/17181H01L2225/06513H01L2225/06517H01L2924/15192H01L2924/15311
    • Enhanced electrostatic discharge (ESD) protection schemes of an integrated circuit in three-dimensional (3D) integrated circuit (ICs) packages, and methods of forming the same are presented in the disclosure. An array of ESD protection devices can be formed in an interposer and placed under one or a plurality of ICs so that a hard block inside an IC on top of the interposer can be connected to an ESD protection device of the array and is protected from ESD. The ESD protection device cell of the array is connected to a Voltage Regulator Module (VRM) which can be placed inside the interposer, on the surface of the interposer, or on the surface of a printed circuit board (PCB). The ESD protection array is of generic nature and can be used with many kinds of ICs to form a three-dimensional IC package. Further embodiments of ESD protection for 3D IC package is disclosed where an ESD protection device inside a first IC 2 can be shared with another IC 1 to protect a hard block within IC 1.
    • 本发明公开了三维(3D)集成电路(IC)封装中集成电路的增强型静电放电(ESD)保护方案及其形成方法。 ESD保护器件的阵列可以形成在插入器中并放置在一个或多个IC下方,使得内插器顶部的IC内部的硬块可以连接到阵列的ESD保护器件并且被保护免受ESD 。 该阵列的ESD保护器件单元连接到一个稳压器模块(VRM),可以放置在插入器内部,插入表面或印刷电路板(PCB)表面上。 ESD保护阵列具有通用性,可与多种IC一起使用,形成三维IC封装。 公开了用于3D IC封装的ESD保护的其它实施例,其中第一IC 2内部的ESD保护装置可以与另一IC 1共享以保护IC 1内的硬块。
    • 10. 发明申请
    • Enhanced ESD Protection of Integrated Circuit in 3DIC package
    • 3DIC封装中集成电路的增强ESD保护
    • US20120182650A1
    • 2012-07-19
    • US13009612
    • 2011-01-19
    • Shyh-An Chi
    • Shyh-An Chi
    • H02H9/00H01L21/50
    • H01L23/60H01L23/49822H01L23/50H01L25/0655H01L25/0657H01L2224/14181H01L2224/16145H01L2224/16225H01L2224/1703H01L2224/17181H01L2225/06513H01L2225/06517H01L2924/15192H01L2924/15311
    • Enhanced electrostatic discharge (ESD) protection schemes of an integrated circuit in three-dimensional (3D) integrated circuit (ICs) packages, and methods of forming the same are presented in the disclosure. An array of ESD protection devices can be formed in an interposer and placed under one or a plurality of ICs so that a hard block inside an IC on top of the interposer can be connected to an ESD protection device of the array and is protected from ESD. The ESD protection device cell of the array is connected to a Voltage Regulator Module (VRM) which can be placed inside the interposer, on the surface of the interposer, or on the surface of a printed circuit board (PCB). The ESD protection array is of generic nature and can be used with many kinds of ICs to form a three-dimensional IC package. Further embodiments of ESD protection for 3D IC package is disclosed where an ESD protection device inside a first IC 2 can be shared with another IC 1 to protect a hard block within IC 1.
    • 本发明公开了三维(3D)集成电路(IC)封装中集成电路的增强型静电放电(ESD)保护方案及其形成方法。 ESD保护器件的阵列可以形成在插入器中并放置在一个或多个IC下方,使得内插器顶部的IC内部的硬块可以连接到阵列的ESD保护器件并且被保护免受ESD 。 该阵列的ESD保护器件单元连接到一个稳压器模块(VRM),可以放置在插入器内部,插入表面或印刷电路板(PCB)表面上。 ESD保护阵列具有通用性,可与多种IC一起使用,形成三维IC封装。 公开了用于3D IC封装的ESD保护的其它实施例,其中第一IC 2内部的ESD保护装置可以与另一IC 1共享以保护IC 1内的硬块。