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1. 发明申请

US20050127405A1 I/O circuit placement method and semiconductor device 失效
标题翻译： I / O电路放置方法和半导体器件
公开(公告)号：US20050127405A1
公开(公告)日：2005-06-16
申请号：US10733095
申请日：2003-12-11
申请人： Wang-Jin Chen , Chen-Teng Fan , Cheng-I Huang , Ya-Yun Liu
发明人： Wang-Jin Chen , Chen-Teng Fan , Cheng-I Huang , Ya-Yun Liu
IPC分类号： G06F9/45 , H01L23/48 , H01L23/52 , H01L27/02 , H01L27/118
CPC分类号： H01L27/11898 , H01L27/0207
摘要： An I/O circuit placement method. In the I/O circuit placement method, at least two rows of I/O circuits are placed on a first side of the chip, and each I/O circuit has a head section and a tail section. The placement direction of the head section and the tail section is perpendicular to the placement direction of the I/O circuits in the rows. The semiconductor further has a core circuit disposed on the chip, wherein the rows of I/O circuits are disposed outside the core circuit and are at the periphery of the chip. Due to the I/O circuit placement in the semiconductor device, the present invention reduces the area of the semiconductor chip and fabrication cost.
摘要翻译：一种I / O电路放置方法。在I / O电路放置方法中，至少两行I / O电路放置在芯片的第一侧上，并且每个I / O电路具有头部和尾部。头部和尾部的放置方向垂直于行中的I / O电路的放置方向。半导体还具有设置在芯片上的核心电路，其中I / O电路行设置在核心电路的外部并且位于芯片的外围。由于半导体器件中的I / O电路布置，本发明减小了半导体芯片的面积和制造成本。

2. 发明授权

US06895540B2 Mux scan cell with delay circuit for reducing hold-time violations 失效
标题翻译：具有延迟电路的Mux扫描单元，以减少持续时间违规
公开(公告)号：US06895540B2
公开(公告)日：2005-05-17
申请号：US10064475
申请日：2002-07-18
申请人： Wang-Jin Chen , Chen-Teng Fan , Cheng-I Huang
发明人： Wang-Jin Chen , Chen-Teng Fan , Cheng-I Huang
IPC分类号： G01R31/3185 , G01R31/28 , G06F9/45 , H01L25/00
CPC分类号： G01R31/318594 , G01R31/318541
摘要： A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.
摘要翻译：多路复用扫描单元包括多路复用器，其具有用于接收原始数据的第一输入节点，用于接收测试数据的第二输入节点，输出节点，选择节点和电连接在第二输入节点和输出节点之间的延迟电路，用于延长测试数据从第二输入节点到输出节点行进的行进时间。复用器扫描单元还包括连接到多路复用器的触发器。利用延迟电路，延长测试数据的行进时间，使得测试数据从第二输入节点行进到输出节点的行进时间模拟原始数据行进通过的行进时间的总和组合逻辑和原始数据从第一输入节点传播到输出节点的行进时间。

3. 发明授权

US07165232B2 I/O circuit placement method and semiconductor device 失效
标题翻译： I / O电路放置方法和半导体器件
公开(公告)号：US07165232B2
公开(公告)日：2007-01-16
申请号：US10733095
申请日：2003-12-11
申请人： Wang-Jin Chen , Chen-Teng Fan , Cheng-I Huang , Ya-Yun Liu
发明人： Wang-Jin Chen , Chen-Teng Fan , Cheng-I Huang , Ya-Yun Liu
IPC分类号： G06F17/50 , H01L29/40
CPC分类号： H01L27/11898 , H01L27/0207
摘要： An I/O circuit placement method. In the I/O circuit placement method, at least two rows of I/O circuits are placed on a first side of the chip, and each I/O circuit has a head section and a tail section. The placement direction of the head section and the tail section is perpendicular to the placement direction of the I/O circuits in the rows. The semiconductor further has a core circuit disposed on the chip, wherein the rows of I/O circuits are disposed outside the core circuit and are at the periphery of the chip. Due to the I/O circuit placement in the semiconductor device, the present invention reduces the area of the semiconductor chip and fabrication cost.
摘要翻译：一种I / O电路放置方法。在I / O电路放置方法中，至少两行I / O电路放置在芯片的第一侧上，并且每个I / O电路具有头部和尾部。头部和尾部的放置方向垂直于行中的I / O电路的放置方向。半导体还具有设置在芯片上的核心电路，其中I / O电路行设置在核心电路的外部并且位于芯片的外围。由于半导体器件中的I / O电路布置，本发明减小了半导体芯片的面积和制造成本。

4. 发明授权

US06978411B2 Memory test system for peak power reduction 失效
标题翻译：用于峰值功率降低的内存测试系统
公开(公告)号：US06978411B2
公开(公告)日：2005-12-20
申请号：US10265700
申请日：2002-10-08
申请人： Cheng-I Huang , Chen-Teng Fan , Wang-Jin Chen , Jyh-Herny Wang
发明人： Cheng-I Huang , Chen-Teng Fan , Wang-Jin Chen , Jyh-Herny Wang
IPC分类号： G11C29/56 , G01R31/28
CPC分类号： G11C29/56012 , G11C29/56
摘要： A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.
摘要翻译：用于峰值功率降低的记忆测试系统。存储器测试系统包括多个存储器，多个存储器内置自检电路和多个延迟单元。每个存储器内置的自检电路包括内置的自检控制器，用于接收时钟信号并产生多个所需的控制信号以测试其中一个存储器。每个延迟单元耦合在两个相邻的内置自检控制器之间。输入到内置自检控制器之一的时钟信号由延迟单元接收以产生延迟的时钟信号，并且延迟单元将延迟的时钟信号输出到另一个。

5. 发明授权

US06380788B1 Programmable clock trunk architecture 失效
标题翻译：可编程时钟中继架构
公开(公告)号：US06380788B1
公开(公告)日：2002-04-30
申请号：US09853179
申请日：2001-05-09
申请人： Chen-Teng Fan , Jyh-Herng Wang , Yu-Wen Tsai , Peng-Chuan Huang
发明人： Chen-Teng Fan , Jyh-Herng Wang , Yu-Wen Tsai , Peng-Chuan Huang
IPC分类号： H03K300
CPC分类号： H03K19/1774 , G06F1/10 , H03K5/15013 , H03K19/1778
摘要： A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at one time, so that the clock signal of a corresponding phase is transferred to the circuit block. The driving forces applied on the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew. Alternately, programmable delay buffers can be used for achieving the same goal.
摘要翻译：一种时钟架构，包括时钟源，多相时钟信号发生器，控制总线，多个时钟信号线以及至少一个电路块。时钟源产生一个全局时钟信号，然后传输到连接到时钟源的多相时钟信号发生器。在接收到全局时钟信号时，连接到控制总线的多相时钟信号发生器根据来自控制总线的信号产生不同相位的时钟信号。每个时钟信号分支传送不同相位的时钟信号中的一个，其中每个时钟信号分支通过电开关单独连接到电路块。一次只有一个开关处于导通状态，使相应相位的时钟信号传送到电路块。连接到时钟源的时钟缓冲器和分支上的时钟缓冲器的驱动力可调，以减少时钟偏移。或者，可以使用可编程延迟缓冲器来实现相同的目标。

6. 发明授权

US07467365B2 Sanity checker for integrated circuits 有权
公开(公告)号：US07467365B2
公开(公告)日：2008-12-16
申请号：US11521095
申请日：2006-09-14
申请人： George H. Chang , Yi-Kan Cheng , Chen-Teng Fan , Chen-Lin Yang , Yung-Chin Hou , Chu-Ping James Wang
发明人： George H. Chang , Yi-Kan Cheng , Chen-Teng Fan , Chen-Lin Yang , Yung-Chin Hou , Chu-Ping James Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising automatically reading one or more netlists, identifying one or more sub-circuits in the netlists isomorphic to at least one of predefined sub-circuits, identifying one or more device parameters for sanity checking the identified sub-circuits, and comparing the identified device parameters against the predefined checking criteria.

7. 发明授权

US06404222B1 Chip capacitance measurement circuit 失效
标题翻译：片式电容测量电路
公开(公告)号：US06404222B1
公开(公告)日：2002-06-11
申请号：US09631342
申请日：2000-08-02
申请人： Chen-Teng Fan , Jyh-Herng Wang
发明人： Chen-Teng Fan , Jyh-Herng Wang
IPC分类号： G01R3126
CPC分类号： G01R27/2605 , G01R31/2639
摘要： A silicon chip capacitance measurement circuit including three pairs of completely matched MOS transistors divided into two symmetrical circuits. Capacitance of a capacitor within the silicon chip is measured using the difference in average charging current flowing from the measurement circuit via a left and a right capacitor. A power supply provides a constant voltage source to the measurement circuit. A current measuring device measures the current flowing from the power supply to the measurement circuit. A signal generator provides a group of three-phase non-overlapping signals to the measurement circuit. The capacitance measurement circuit is able to limit measurement error due to the return of different size negative currents leading to the transient switching of MOS transistors in the current measurement device so that accuracy of capacitance measurement improves.
摘要翻译：一种硅芯片电容测量电路，包括三对完全匹配的MOS晶体管，分为两个对称电路。使用从测量电路经由左右电容器流出的平均充电电流的差异来测量硅芯片内的电容器的电容。电源为测量电路提供恒定电压源。电流测量装置测量从电源流向测量电路的电流。信号发生器向测量电路提供一组三相不重叠的信号。电容测量电路能够限制由于不同尺寸的负电流的返回导致的测量误差，导致电流测量装置中的MOS晶体管的瞬态切换，从而提高了电容测量的精度。

8. 发明申请

US20080072191A1 Sanity checker for integrated circuits 有权
标题翻译：集成电路的检查器
公开(公告)号：US20080072191A1
公开(公告)日：2008-03-20
申请号：US11521095
申请日：2006-09-14
申请人： George H. Chang , Yi-Kan Cheng , Chen-Teng Fan , Chen-Lin Yang , Yung-Chin Hou , Chu-Ping James Wang
发明人： George H. Chang , Yi-Kan Cheng , Chen-Teng Fan , Chen-Lin Yang , Yung-Chin Hou , Chu-Ping James Wang
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising automatically reading one or more netlists, identifying one or more sub-circuits in the netlists isomorphic to at least one of predefined sub-circuits, identifying one or more device parameters for sanity checking the identified sub-circuits, and comparing the identified device parameters against the predefined checking criteria.
摘要翻译：本发明公开了一种基于具有至少一个预定义的检查标准的一个或多个预定义子电路的完整性检查集成电路（IC）设计的方法，所述方法包括自动读取一个或多个网表，识别所述子电路中的一个或多个子电路网表与至少一个预定义的子电路同构，识别一个或多个设备参数，以便确认所识别的子电路，以及将所识别的设备参数与预定义的检查标准进行比较。

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