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1. 发明授权

US08911482B2 Interlocking bone plate system 有权
标题翻译：联锁骨板系统
公开(公告)号：US08911482B2
公开(公告)日：2014-12-16
申请号：US13418668
申请日：2012-03-13
申请人： Cheng-Hung Lee , Chih-Han Chang , Chih-Kun Hsiao , Kui-Chou Huang , Chih-Hui Chen
发明人： Cheng-Hung Lee , Chih-Han Chang , Chih-Kun Hsiao , Kui-Chou Huang , Chih-Hui Chen
IPC分类号： A61B17/80 , A61B17/58 , A61B17/72 , A61B17/86
CPC分类号： A61B17/7283 , A61B17/8057 , A61B17/8061 , A61B17/8605 , A61B17/8625
摘要： An interlocking bone plate system includes an outer bone plate for being arranged outside a broken bone, an inner bone plate for being installed inside the medullary cavity of the broken bone, and screws for being inserted through and engaged with the outer bone plate and the broken bone and then engaged with the inner bone plate so as to interlock the out and inner bone plates together. The inner bone plate provides an added support in addition to the support provided by the outer bone plate, enhancing the structural strength of the whole bone fixation structure and lowering the risk of failed surgery.
摘要翻译：互锁骨板系统包括用于布置在骨骨外侧的外骨板，用于安装在破骨的髓腔内部的内骨板，以及用于插入并与外骨板接合的螺钉和破碎的骨骨，然后与内骨板接合，以将外骨板和内骨板互锁在一起。内骨板除了外骨板提供的支撑外，还增加了支撑，提高了整个骨固定结构的结构强度，降低了手术失败的风险。

2. 发明授权

US09099168B2 Method for extending word-line pulses 有权
标题翻译：扩展字线脉冲的方法
公开(公告)号：US09099168B2
公开(公告)日：2015-08-04
申请号：US13616377
申请日：2012-09-14
申请人： Hsu-Shun Chen , Cheng-Hung Lee , Hong-Chen Cheng , Chung-Yi Wu
发明人： Hsu-Shun Chen , Cheng-Hung Lee , Hong-Chen Cheng , Chung-Yi Wu
IPC分类号： G11C8/08 , G11C11/413
CPC分类号： G11C8/08 , G11C11/413
摘要： An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.
摘要翻译：集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。多个电流通路的电流反映了电流跟踪电路的电流。电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

3. 发明授权

US07613054B2 SRAM device with enhanced read/write operations 有权
标题翻译：具有增强的读/写操作的SRAM器件
公开(公告)号：US07613054B2
公开(公告)日：2009-11-03
申请号：US11924437
申请日：2007-10-25
申请人： Cheng-Hung Lee , Ping-Wei Wang , Ching-Wei Wu , Shu-Hsuan Lin , Feng-Ming Chang , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ping-Wei Wang , Ching-Wei Wu , Shu-Hsuan Lin , Feng-Ming Chang , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , H01L27/1104
摘要： An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.
摘要翻译： SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

4. 发明授权

US07408830B2 Dynamic power supplies for semiconductor devices 有权
标题翻译：用于半导体器件的动态电源
公开(公告)号：US07408830B2
公开(公告)日：2008-08-05
申请号：US11593778
申请日：2006-11-07
申请人： Cheng-Hung Lee
发明人： Cheng-Hung Lee
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： This invention discloses a power supply management circuit which comprises at least one switching circuit coupled between a power supply and a power recipient circuit, and at least one voltage booster circuit coupled between a control circuit and the power recipient circuit, wherein the control circuit is configured to turn on-or-off the switching circuit, and to activate or de-activate the voltage booster circuit.
摘要翻译：本发明公开了一种电源管理电路，其包括耦合在电源和受电电路之间的至少一个开关电路，以及耦合在控制电路和电源接收电路之间的至少一个升压电路，其中所述控制电路被配置打开或关闭开关电路，并激活或去激活升压电路。

5. 发明授权

US08675439B2 Bit line voltage bias for low power memory design 有权
标题翻译：用于低功耗存储器设计的位线电压偏置
公开(公告)号：US08675439B2
公开(公告)日：2014-03-18
申请号：US13271353
申请日：2011-10-12
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C7/12 , G11C11/419
摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.
摘要翻译：在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和响应于控制信号的待机模式。位线偏置电路控制在处于睡眠模式时使位线浮动的电压。用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

6. 发明申请

US20130277794A1 Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps 有权
标题翻译：调整使用微型轰击发射射频信号的效率
公开(公告)号：US20130277794A1
公开(公告)日：2013-10-24
申请号：US13841577
申请日：2013-03-15
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Cheng-Hung Lee , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Cheng-Hung Lee , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01L23/60
CPC分类号： H01L23/60 , H01L23/66 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2223/6677 , H01L2224/0401 , H01L2224/05023 , H01L2224/05073 , H01L2224/05147 , H01L2224/05567 , H01L2224/05568 , H01L2224/05655 , H01L2224/13083 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/17517 , H01L2224/81455 , H01L2225/06513 , H01L2924/00014 , H01L2924/01029 , H01L2924/13091 , H01L2924/14 , H01L2924/1421 , H01L2924/15192 , H01L2924/15311 , H01L2924/19104 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2224/131 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump.
摘要翻译：一种器件包括：裸片，包括主电路和耦合到主电路的第一焊盘。包括第二垫的工件被结合到模具。第一多个微凸块在第一和第二焊盘之间串联电耦合。多个微型凸块中的每一个包括连接模具的第一端和连接工件的第二端。微凸块与模具和工件结合。第二焊盘电耦合到微凸起。

7. 发明授权

US07952911B2 SRAM cell array structure 有权
标题翻译： SRAM单元阵列结构
公开(公告)号：US07952911B2
公开(公告)日：2011-05-31
申请号：US12111905
申请日：2008-04-29
申请人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C11/419
摘要： This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元阵列结构，其包括耦合到一列SRAM单元的第一和第二位线，第一和第二位线基本上彼此平行并由第一金属层，并且第一导线被放置在第一和第二位线之间并跨越SRAM单元的列而不与其形成导电耦合，第一导电线也由第一金属层形成。

8. 发明申请

US20110242904A1 Read Only Memory and Operating Method Thereof 有权
标题翻译：只读存储器及其操作方法
公开(公告)号：US20110242904A1
公开(公告)日：2011-10-06
申请号：US12983985
申请日：2011-01-04
申请人： Ching-Wei Wu , Cheng-Hung Lee , He-Zhou Wan , Wei-Yang Jiang
发明人： Ching-Wei Wu , Cheng-Hung Lee , He-Zhou Wan , Wei-Yang Jiang
IPC分类号： G11C16/08
CPC分类号： G11C8/08 , G11C17/14
摘要： A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages.
摘要翻译：提供只读存储器（ROM）及其操作方法。只读存储器包括：控制电路，由第一电源供电，用于在第一电压范围内输出控制信号; 电压移位器，用于将控制信号的振幅扩大到第二电压范围; 由具有比第一电源的电压高的第二电源供电的字线驱动器，用于根据扩展至的只读存储单元阵列的多个字线中的一个字线驱动处于第二电压范围内; 以及用于连接多个位线以读出消息的输入/输出电路。

9. 发明授权

US07913215B2 Memory macro with irregular edge cells 有权
标题翻译：具有不规则边缘单元格的内存宏
公开(公告)号：US07913215B2
公开(公告)日：2011-03-22
申请号：US11493405
申请日：2006-07-26
申请人： Chung-Cheng Chou , Cheng-Hung Lee
发明人： Chung-Cheng Chou , Cheng-Hung Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A memory macro includes a first set of cells disposed in a first area of a memory array, and a second set of cells, which differ from the first set of cells in physical dimensions, disposed at an edge of the first area for improving robustness of the cells at the edge of the memory array.
摘要翻译：存储器宏包括设置在存储器阵列的第一区域中的第一组单元，以及设置在第一区域的边缘处的与物理尺寸的第一组单元不同的第二组单元，用于改善第一区域的鲁棒性存储器阵列边缘的单元格。

10. 发明申请

US20080229161A1 MEMORY PRODUCTS AND MANUFACTURING METHODS THEREOF 审中-公开
标题翻译：记忆产品及其制造方法
公开(公告)号：US20080229161A1
公开(公告)日：2008-09-18
申请号：US11686996
申请日：2007-03-16
申请人： Cheng-Hung Lee , Ching-Wei Wu , Chung-Cheng Chou , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ching-Wei Wu , Chung-Cheng Chou , Hung-Jen Liao
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/70 , G11C29/80 , G11C2029/5004 , H01L22/22 , H01L27/1052
摘要： Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if the memory cell is determined to have experienced Vccmin failure.
摘要翻译：内存产品及其制造方法。存储器产品包括至少一个存储器单元和至少一个冗余存储单元。存储单元和冗余存储单元具有不同的物理或电子特性。如果确定存储器单元已经经历Vccmin故障，则冗余存储器单元被用作存储器单元的修复方案。

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