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1. 发明申请

US20110254127A1 METHOD AND DEVICE FOR A DRAM CAPACITOR HAVING LOW DEPLETION RATIO 有权
标题翻译：具有低剥离比率的DRAM电容器的方法和装置
公开(公告)号：US20110254127A1
公开(公告)日：2011-10-20
申请号：US13078917
申请日：2011-04-01
申请人： CHENG YANG , Bo Tao , Jason Luo , Jingang Wu
发明人： CHENG YANG , Bo Tao , Jason Luo , Jingang Wu
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L28/84 , H01L28/82
摘要： A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.
摘要翻译：一种制造具有低耗尽率电容器的半导体集成电路器件的方法，包括：在多晶硅上形成半球状晶粒（HSG）; 在磷化氢气体中掺杂半球形多晶硅; 并在850℃下快速热氧化掺杂的半球晶粒状多晶硅10秒。该方法还包括将快速热氧化的半球状多晶硅氮化并在氮化硅层上沉积氧化铝膜。提供了根据所公开的制造方法具有低耗尽率电容器的半导体集成电路器件。

2. 发明授权

US08426286B2 Method and device for a DRAM capacitor having low depletion ratio 有权
标题翻译：具有低耗尽率的DRAM电容器的方法和装置
公开(公告)号：US08426286B2
公开(公告)日：2013-04-23
申请号：US13078917
申请日：2011-04-01
申请人： Cheng Yang , Bo Tao , Jason Luo , Jingang Wu
发明人： Cheng Yang , Bo Tao , Jason Luo , Jingang Wu
IPC分类号： H01L21/20
CPC分类号： H01L28/84 , H01L28/82
摘要： A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.
摘要翻译：一种制造具有低耗尽率电容器的半导体集成电路器件的方法，包括：在多晶硅上形成半球状晶粒（HSG）; 在磷化氢气体中掺杂半球形多晶硅; 并在850℃下快速热氧化掺杂的半球晶粒状多晶硅10秒。该方法还包括将快速热氧化的半球状多晶硅氮化并在氮化硅层上沉积氧化铝膜。提供了根据所公开的制造方法具有低耗尽率电容器的半导体集成电路器件。

3. 发明授权

US07534711B2 System and method for direct etching 有权
标题翻译：用于直接蚀刻的系统和方法
公开(公告)号：US07534711B2
公开(公告)日：2009-05-19
申请号：US11615972
申请日：2006-12-23
申请人： Jingang Wu , Fei Luo , Guanqie Gao , Cheng Yang
发明人： Jingang Wu , Fei Luo , Guanqie Gao , Cheng Yang
IPC分类号： H01L21/20
CPC分类号： H01L21/76802
摘要： System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a substrate having a contact region, which is provided between a first word line and a second word line. The contact region has an overlying plug structure, which is provided within a thickness of a first dielectric layer. The first dielectric layer includes a portion overlying the plug structure. The first dielectric layer has a planarized surface region. The method also includes a step for forming a first line and a second line and a space provided between the first word line and the second world line. The space is provided within a region overlying the plug structure.
摘要翻译：用于直接蚀刻的系统和方法根据实施例，本发明提供一种用于制造集成电路器件的方法。该方法包括提供具有接触区域的基板的步骤，该接触区域设置在第一字线和第二字线之间。接触区域具有覆盖的塞子结构，其设置在第一介电层的厚度内。第一电介质层包括覆盖插塞结构的部分。第一电介质层具有平坦化的表面区域。该方法还包括用于形成第一线和第二线以及设置在第一字线和第二世界线之间的空间的步骤。该空间设置在覆盖插头结构的区域内。

4. 发明申请

US20080146030A1 SYSTEM AND METHOD FOR DIRECT ETCHING 有权
标题翻译：用于直接蚀刻的系统和方法
公开(公告)号：US20080146030A1
公开(公告)日：2008-06-19
申请号：US11615972
申请日：2006-12-23
申请人： Jingang Wu , Fei Luo , Guanqie Gao , Cheng Yang
发明人： Jingang Wu , Fei Luo , Guanqie Gao , Cheng Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/76802
摘要： System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a substrate having a contact region, which is provided between a first word line and a second word line. The contact region has an overlying plug structure, which is provided within a thickness of a first dielectric layer. The first dielectric layer includes a portion overlying the plug structure. The first dielectric layer has a planarized surface region. The method also includes a step for forming a first line and a second line and a space provided between the first word line and the second world line. The space is provided within a region overlying the plug structure.
摘要翻译：用于直接蚀刻的系统和方法根据实施例，本发明提供一种用于制造集成电路器件的方法。该方法包括提供具有接触区域的基板的步骤，该接触区域设置在第一字线和第二字线之间。接触区域具有覆盖的塞子结构，其设置在第一介电层的厚度内。第一电介质层包括覆盖插塞结构的部分。第一电介质层具有平坦化的表面区域。该方法还包括用于形成第一线和第二线以及设置在第一字线和第二世界线之间的空间的步骤。该空间设置在覆盖插头结构的区域内。

5. 发明授权

US08513075B2 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08513075B2
公开(公告)日：2013-08-20
申请号：US13306969
申请日：2011-11-29
申请人： Yonggen He , Jingang Wu , Haibiao Yao
发明人： Yonggen He , Jingang Wu , Haibiao Yao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864
摘要： A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.
摘要翻译：一种用于制造半导体器件的制造方法，包括在半导体衬底上沉积间隔物材料，所述衬底包括NMOS区域和PMOS区域，每个区域都形成有栅极。该方法还包括用第一掩模覆盖NMOS区域，通过蚀刻间隔物材料形成用于PMOS栅极的间隔物，通过蚀刻在PMOS区域中形成凹陷，并在其中生长具有原位掺杂B的SiGe或SiGe PMOS区域的凹部以形成PMOS源极/漏极区域。该方法还包括在凹部上执行各向异性湿蚀刻。在用原位掺杂的B生长SiGE或SiGe之后，该方法还包括用第二掩模覆盖PMOS区，并通过蚀刻间隔物材料形成NMOS栅的间隔物。用于PMOS和NMOS栅极的间隔物具有不同的临界尺寸。

6. 发明授权

US07259027B2 Low energy dose monitoring of implanter using implanted wafers 有权
标题翻译：使用植入晶片的注入机的低能量剂量监测
公开(公告)号：US07259027B2
公开(公告)日：2007-08-21
申请号：US10773728
申请日：2004-02-06
申请人： Jingang Wu , Jianpeng Song , Minggang Chang , Chinte Huang
发明人： Jingang Wu , Jianpeng Song , Minggang Chang , Chinte Huang
IPC分类号： G01R31/26 , H01L21/00
CPC分类号： H01L22/20 , H01L21/26506 , H01L21/26513 , H01L22/34
摘要： A method for processing semiconductor wafers, e.g., silicon. The method includes providing a monitor wafer, which is made of a crystalline material. The method includes introducing a plurality of particles within a depth of the material, whereupon the plurality of particles cause the crystalline material to be in an amorphous state. The method also includes introducing a plurality of dopant particles into a selected depth of the crystalline material in the amorphous state using an implantation tool. The amorphous state traps the dopant particles. The method includes subjecting the monitor wafer including the plurality of particles and dopant particles into thermal anneal process to activate the dopant. The sheet resistivity is measured. The method operates the implantation tool using one or more production wafers if the dose of the dopant particles in the monitor water is within a tolerance of a specification limit.
摘要翻译：一种半导体晶片（例如硅）的处理方法。该方法包括提供由结晶材料制成的监测晶片。该方法包括在材料的深度内引入多个颗粒，于是多个颗粒导致结晶材料处于非晶状态。该方法还包括使用注入工具将多个掺杂剂颗粒引入晶体材料的非晶状态的选定深度。非晶状态捕获掺杂剂颗粒。该方法包括将包括多个颗粒和掺杂剂颗粒的监测晶片进行热退火处理以激活掺杂剂。测量薄层电阻率。如果监测水中的掺杂剂颗粒的剂量在规定限度的公差内，则该方法使用一个或多个生产晶片来操作植入工具。

7. 发明授权

US06962884B2 Monitoring low temperature rapid thermal anneal process using implanted wafers 有权
标题翻译：使用植入晶片监测低温快速热退火工艺
公开(公告)号：US06962884B2
公开(公告)日：2005-11-08
申请号：US10743689
申请日：2003-12-19
申请人： Jingang Wu , Amy Liu , Tony Wang , Dennis Huang
发明人： Jingang Wu , Amy Liu , Tony Wang , Dennis Huang
IPC分类号： H01L21/265 , H01L21/324 , H01L21/66 , H01L23/544 , H01L21/26
CPC分类号： H01L22/20 , H01L21/26513 , H01L21/324 , H01L22/34
摘要： A method for processing integrated circuit devices. The method includes providing a monitor wafer, which comprising a silicon material. The method introduces a plurality of particles within a depth of the silicon material. The plurality of particles have a reduced activation energy within the silicon material. The method subjects the monitor wafer including the plurality of particles into a rapid thermal anneal process. The method includes applying the rapid thermal anneal process at a first state including a first temperature. The first temperature is within a range defined as a low temperature range, which is less than 650 Degrees Celsius. The method includes removing the monitor wafer and measuring a sheet resistivity of the monitor wafer. The method also determines the first temperature within a tolerance of less than 2 percent across the monitor wafer. The method operates the rapid thermal process using a plurality of production wafers if the first temperature is within a tolerance of a specification temperature.
摘要翻译：一种用于处理集成电路器件的方法。该方法包括提供包括硅材料的监测晶片。该方法在硅材料的深度内引入多个颗粒。多个颗粒在硅材料内具有降低的活化能。该方法将包括多个颗粒的监测晶片进行快速热退火处理。该方法包括将快速热退火工艺应用于包括第一温度的第一状态。第一个温度在一个定义为低于650摄氏度的低温范围的范围内。该方法包括移除监测晶片并测量监测晶片的薄层电阻率。该方法还确定跨越监视器晶片的容差内的第一温度小于2％。如果第一温度在规定温度的公差范围内，则该方法使用多个生产晶片进行快速热处理。

8. 发明授权

US08451646B2 Resistive random access memory and the method of operating the same 有权
标题翻译：电阻随机存取存储器及其操作方法
公开(公告)号：US08451646B2
公开(公告)日：2013-05-28
申请号：US12854491
申请日：2010-08-11
申请人： Min-hwa Chi , Xiaohui Huang , Lijun Song , Jingang Wu , Deyuan Xiao
发明人： Min-hwa Chi , Xiaohui Huang , Lijun Song , Jingang Wu , Deyuan Xiao
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/003 , G11C2013/0071 , G11C2013/0078 , G11C2013/0083 , G11C2213/78 , G11C2213/79
摘要： A resistive random access memory utilizing gate induced drain leakage current as the read operation current and the write operation current and a method of operation the same, wherein the resistive random access memory including a plurality of arrayed memory cells, a plurality of bit-lines and a plurality word-lines, each memory cell including: a switching resistor having a first terminal and a second terminal, the first terminal of the switching resistor being connected to one bit-line; and a MOSFET being connected to the second terminal and having a gate, a source, a drain and a substrate, the gate being connected to one word-line, the read operation current and the write operation current of the memory cell being gate induced drain leakage current of the MOSFET. The RRAM array presented in this invention has superior scalability for resistors as well as transistors, which leads to a memory array with higher density.
摘要翻译：一种利用栅极感应漏极漏电流作为读操作电流和写操作电流的电阻随机存取存储器及其操作方法，其中所述电阻随机存取存储器包括多个阵列存储单元，多个位线和多个字线，每个存储单元包括：具有第一端子和第二端子的开关电阻器，所述开关电阻器的第一端子连接到一个位线; 以及连接到第二端子并且具有栅极，源极，漏极和衬底的MOSFET，栅极连接到一个字线，存储器单元的读取操作电流和写入操作电流是栅极感应漏极 MOSFET的漏电流。在本发明中呈现的RRAM阵列对于电阻器和晶体管具有优异的可扩展性，这导致具有更高密度的存储器阵列。

9. 发明授权

US6048820A Copper-based catalyst and method for production thereof 失效
标题翻译：铜基催化剂及其制造方法
公开(公告)号：US6048820A
公开(公告)日：2000-04-11
申请号：US37011
申请日：1998-03-09
申请人： Masami Takeuchi , Hirotaka Mabuse , Taiki Watanabe , Michiaki Umeno , Takashi Matsuda , Kozo Mori , Kenji Ushikoshi , Jamil Toyir , Shengcheng Luo , Jingang Wu , Masahiro Saito
发明人： Masami Takeuchi , Hirotaka Mabuse , Taiki Watanabe , Michiaki Umeno , Takashi Matsuda , Kozo Mori , Kenji Ushikoshi , Jamil Toyir , Shengcheng Luo , Jingang Wu , Masahiro Saito
IPC分类号： C01B3/26 , B01J23/80 , B01J23/835 , B01J23/89 , B01J37/02 , B01J37/03 , B01J37/08 , C01B3/22 , C01B3/32 , C07B61/00 , C07C29/154 , C07C31/04 , B01J21/08 , B01J21/12 , B01J21/14 , B01J23/72
CPC分类号： C07C29/154 , B01J23/80 , B01J23/825 , B01J37/0236 , C01B3/326 , B01J2523/00 , C01B2203/1041 , C01B2203/1064 , C01B2203/1076 , C01B2203/1082 , Y02P20/52
摘要： The invention relates to a copper-based catalyst with high activity and a long catalyst life and to a method of producing the catalyst. This catalyst essentially comprises copper oxide, zinc oxide, aluminum oxide, and silicon oxide and optionally containing zirconium oxide, gallium oxide, and palladium oxide, wherein with the total weight of the catalyst being taken as 100%, the above oxides account for, in the order mentioned, 20-60 weight %, 10-50 weight %, 2-10 weight %, 0.3-0.9 weight %, 0-40 weight %, 0-10 weight %, and 0-10 weight %, respectively, and the silicon oxide mentioned above has been derived from colloidal silica or dissolved silica in water, which catalyst has been subjected to calcination at 480-690.degree. C.
摘要翻译：本发明涉及一种活性高且催化剂寿命长的铜基催化剂及其制备方法。该催化剂基本上包含氧化铜，氧化锌，氧化铝和氧化硅，并且任选地含有氧化锆，氧化镓和氧化钯，其中催化剂的总重量为100％，上述氧化物占所述顺序分别为20-60重量％，10-50重量％，2-10重量％，0.3-0.9重量％，0-40重量％，0-10重量％和0-10重量％，以及上述氧化硅已经从胶体二氧化硅或溶解的二氧化硅在水中得到，该催化剂已经在480-690℃下进行煅烧。

10. 发明申请

US20050142671A1 Low energy dose monitoring of implanter using implanted wafers 有权
标题翻译：使用植入晶片的注入机的低能量剂量监测
公开(公告)号：US20050142671A1
公开(公告)日：2005-06-30
申请号：US10773728
申请日：2004-02-06
申请人： Jingang Wu , Jianpeng Song , Minggang Chang , Chinte Huang
发明人： Jingang Wu , Jianpeng Song , Minggang Chang , Chinte Huang
IPC分类号： G01R31/26 , H01J37/317 , H01L21/265 , H01L21/42 , H01L21/66 , H01L21/82 , H01L23/544
CPC分类号： H01L22/20 , H01L21/26506 , H01L21/26513 , H01L22/34
摘要： A method for processing semiconductor wafers, e.g., silicon. The method includes providing a monitor wafer, which is made of a crystalline material. The method includes introducing a plurality of particles within a depth of the material, whereupon the plurality of particles cause the crystalline material to be in an amorphous state. The method also includes introducing a plurality of dopant particles into a selected depth of the crystalline material in the amorphous state using an implantation tool. The amorphous state traps the dopant particles. The method includes subjecting the monitor wafer including the plurality of particles and dopant particles into thermal anneal process to activate the dopant. The sheet resistivity is measured. The method operates the implantation tool using one or more production wafers if the dose of the dopant particles in the monitor water is within a tolerance of a specification limit.
摘要翻译：一种半导体晶片（例如硅）的处理方法。该方法包括提供由结晶材料制成的监测晶片。该方法包括在材料的深度内引入多个颗粒，于是多个颗粒导致结晶材料处于非晶状态。该方法还包括使用注入工具将多个掺杂剂颗粒引入晶体材料的非晶状态的选定深度。非晶状态捕获掺杂剂颗粒。该方法包括将包括多个颗粒和掺杂剂颗粒的监测晶片进行热退火处理以激活掺杂剂。测量薄层电阻率。如果监测水中的掺杂剂颗粒的剂量在规定限度的公差内，则该方法使用一个或多个生产晶片来操作植入工具。

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