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1. 发明申请

US20070229115A1 Method and apparatus for correcting duty cycle error in a clock distribution network 审中-公开
标题翻译：用于校正时钟分配网络中的占空比误差的方法和装置
公开(公告)号：US20070229115A1
公开(公告)日：2007-10-04
申请号：US11339124
申请日：2006-01-25
申请人： Charlie Hwang , Phillip Restle , Michael Thomson
发明人： Charlie Hwang , Phillip Restle , Michael Thomson
IPC分类号： H03M7/00 , H03K19/00
CPC分类号： H03K5/1565 , G06F1/10 , H03K5/065
摘要： A clock distribution network for distributing a repetitive timing signal throughout an integrated circuit, the timing signal being within a range of frequencies about a first frequency, includes multiple buffer circuits and at least one conductive segment connecting one of the buffers to another of the buffers. The conductive segment has a length selected so as to be less than a quarter-wave resonance length of the conductive segment at the first frequency to thereby achieve duty cycle correction.
摘要翻译：一种用于在整个集成电路中分配重复定时信号的时钟分配网络，定时信号在大约关于第一频率的频率范围内，包括多个缓冲器电路和至少一个将缓冲器之一连接到另一个缓冲器的导电段。导电段的长度被选择为小于第一频率处的导电段的四分之一波长的谐振长度，从而实现占空比校正。

2. 发明申请

US20070103141A1 DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE 审中-公开
标题翻译：用于测量和维护平衡时间周期的占空比测量电路
公开(公告)号：US20070103141A1
公开(公告)日：2007-05-10
申请号：US11619475
申请日：2007-01-03
申请人： Robert Dixon , Robert Franch , Phillip Restle
发明人： Robert Dixon , Robert Franch , Phillip Restle
IPC分类号： G06M1/10
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318594
摘要： A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
摘要翻译：用于测量片上全局时钟的占空比不确定性的电路和方法。全局时钟提供给本地时钟缓冲器的延迟线。延迟线抽头（变频器输出）是由本地时钟缓冲器计时的寄存器的输入。寄存器捕获时钟边沿，这些边沿被过滤以识别每个边缘的单个位置。边缘之间的空间不平衡表明占空比不平衡。上/下信号由任何不平衡产生，并传递到锁相环以调整平衡。

3. 发明申请

US20050107970A1 Built in self test circuit for measuring total timing uncertainty in a digital data path 有权
标题翻译：内置自检电路，用于测量数字数据路径中的总时序不确定度
公开(公告)号：US20050107970A1
公开(公告)日：2005-05-19
申请号：US10712925
申请日：2003-11-13
申请人： Robert Franch , William Huott , Norman James , Phillip Restle , Timothy Skergan
发明人： Robert Franch , William Huott , Norman James , Phillip Restle , Timothy Skergan
IPC分类号： G01R31/317 , G01R31/3185 , G06F19/00
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
摘要翻译：用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。延迟线抽头（逆变器输出）是由互补时钟对计时的寄存器的输入，以通过延迟线捕获启动时钟的进程，并识别出该进程中的任何变化（例如抖动，VDD噪声）。可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。

4. 发明申请

US20050104646A1 Clock gated power supply noise compensation 失效
标题翻译：时钟门控电源噪声补偿
公开(公告)号：US20050104646A1
公开(公告)日：2005-05-19
申请号：US10712926
申请日：2003-11-13
申请人： Phillip Restle
发明人： Phillip Restle
IPC分类号： G06F1/10 , H03K5/1252 , H03K5/153 , H03L5/00 , H03L7/00
CPC分类号： G06F1/10 , H03K5/1252
摘要： A supply noise compensation circuit. The supply noise compensation circuit senses the onset of dI/dt noise events on a supply line and selectively gates off/forces on a chip clock to chip circuits.
摘要翻译：电源噪声补偿电路。电源噪声补偿电路检测电源线上dI / dt噪声事件的开始，并选择性地切断芯片时钟到芯片电路的关断/势力。

5. 发明申请

US20070209028A1 RESONANT TREE DRIVEN CLOCK DISTRIBUTION GRID 失效
标题翻译：共振树驱动时钟分配网
公开(公告)号：US20070209028A1
公开(公告)日：2007-09-06
申请号：US11740479
申请日：2007-04-26
申请人： Phillip Restle
发明人： Phillip Restle
IPC分类号： G06F17/50
CPC分类号： G06F1/10
摘要： An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.
摘要翻译：用于在集成电路中分配时钟信号的集成电路（IC），IC组件和电路包括其中具有至少一个导体的电容时钟分配电路。在集成电路的金属层中形成至少一个电感器，并且耦合到时钟分配电路。通常以分布在整个集成电路中的多个螺旋电感器的形式的电感器提供选择为在谐振时与电容时钟分配电路谐振的电感值，降低功率消耗，同时可以提高歪斜和抖动性能。

6. 发明授权

US07117455B2 System and method for derivative-free optimization of electrical circuits 失效
标题翻译：无电路优化电路的系统和方法
公开(公告)号：US07117455B2
公开(公告)日：2006-10-03
申请号：US10626762
申请日：2003-07-24
申请人： Steven G. Walker , Chandramouli Visweswariah , Katya Scheinberg , Phillip Restle
发明人： Steven G. Walker , Chandramouli Visweswariah , Katya Scheinberg , Phillip Restle
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/505
摘要： The present invention is a system and method for optimizing electrical circuits by means of derivative-free optimization. Tunable parameters such as component values, transistor sizes or model parameters are automatically adjusted to obtain an optimal circuit. Any method of measuring the performance of the circuit, including computer simulation, can be incorporated into the optimization technique, with no derivative requirements. An arbitrary continuous optimization problem can be posed, including an objective function, equality and inequality constraints, and simple bounds on the tunable parameters. The optimization technique is efficient and guarantees that it will find a locally optimal solution from any starting point. Further, the procedure includes a method of automatically recovering from electrical failure to enable automatic and productive circuit optimization. A set of measurement widgets is provided to automatically introduce the checking required to recover from electrical failure. The automated circuit optimization leads to higher quality circuits, increases designer productivity, results in a better understanding of the tradeoffs inherent in the circuit and lifts the thinking of the circuit designer to a higher level.
摘要翻译：本发明是通过无衍生优化优化电路的系统和方法。可调参数（如元件值，晶体管尺寸或型号参数）会自动调整以获得最佳电路。任何测量电路性能的方法，包括计算机仿真，都可以纳入优化技术，无需衍生要求。可以提出任意的连续优化问题，包括目标函数，等式和不等式约束以及可调参数的简单界限。优化技术是有效的，并保证从任何起点找到局部最优解。此外，该过程包括从电故障自动恢复以实现自动和生产性电路优化的方法。提供一组测量小部件，以自动引入从电气故障中恢复所需的检查。自动化电路优化导致更高质量的电路，提高设计人员的生产力，从而更好地了解电路固有的折中，并将电路设计师的思维提升到更高的水平。

7. 发明申请

US20050114820A1 Resonant tree driven clock distribution grid 失效
标题翻译：共振树驱动时钟分配网格
公开(公告)号：US20050114820A1
公开(公告)日：2005-05-26
申请号：US10720564
申请日：2003-11-24
申请人： Phillip Restle
发明人： Phillip Restle
IPC分类号： G06F1/04 , G06F1/10 , G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/15
CPC分类号： G06F1/10
摘要： An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.
摘要翻译：用于在集成电路中分配时钟信号的集成电路（IC），IC组件和电路包括其中具有至少一个导体的电容时钟分配电路。在集成电路的金属层中形成至少一个电感器，并且耦合到时钟分配电路。通常以分布在整个集成电路中的多个螺旋电感器的形式的电感器提供选择为在谐振时与电容时钟分配电路谐振的电感值，降低功率消耗，同时可以提高歪斜和抖动性能。

8. 发明申请

US20050022141A1 System and method for derivative-free optimization of electrical circuits 失效
标题翻译：无电路优化电路的系统和方法
公开(公告)号：US20050022141A1
公开(公告)日：2005-01-27
申请号：US10626762
申请日：2003-07-24
申请人： Steven Walker , Chandramouli Visweswariah , Katya Scheinberg , Phillip Restle
发明人： Steven Walker , Chandramouli Visweswariah , Katya Scheinberg , Phillip Restle
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/505
摘要： The present invention is a system and method for optimizing electrical circuits by means of derivative-free optimization. Tunable parameters such as component values, transistor sizes or model parameters are automatically adjusted to obtain an optimal circuit. Any method of measuring the performance of the circuit, including computer simulation, can be incorporated into the optimization technique, with no derivative requirements. An arbitrary continuous optimization problem can be posed, including an objective function, equality and inequality constraints, and simple bounds on the tunable parameters. The optimization technique is efficient and guarantees that it will find a locally optimal solution from any starting point. Further, the procedure includes a method of automatically recovering from electrical failure to enable automatic and productive circuit optimization. A set of measurement widgets is provided to automatically introduce the checking required to recover from electrical failure. The automated circuit optimization leads to higher quality circuits, increases designer productivity, results in a better understanding of the tradeoffs inherent in the circuit and lifts the thinking of the circuit designer to a higher level.
摘要翻译：本发明是通过无衍生优化优化电路的系统和方法。可调参数（如元件值，晶体管尺寸或型号参数）会自动调整以获得最佳电路。任何测量电路性能的方法，包括计算机仿真，都可以纳入优化技术，无需衍生要求。可以提出任意的连续优化问题，包括目标函数，等式和不等式约束以及可调参数的简单界限。优化技术是有效的，并保证从任何起点找到局部最优解。此外，该过程包括从电故障自动恢复以实现自动和生产性电路优化的方法。提供了一组测量小部件，以自动引入从电气故障中恢复所需的检查。自动化电路优化导致更高质量的电路，提高设计人员的生产力，从而更好地了解电路固有的折中，并将电路设计师的思维提升到更高的水平。

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