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1. 发明授权

US06748563B1 Method and apparatus for testing path delays in a high-speed boundary scan implementation 失效
标题翻译：用于测试高速边界扫描实现中的路径延迟的方法和装置
公开(公告)号：US06748563B1
公开(公告)日：2004-06-08
申请号：US09704956
申请日：2000-11-02
申请人： Johnny James LeBlanc , Timothy Skergan
发明人： Johnny James LeBlanc , Timothy Skergan
IPC分类号： G11R3128
CPC分类号： G01R31/31858
摘要： A method and apparatus for testing path delays in a high-speed boundary scan implementation overcomes limitations imposed by pipelined high-speed clocking architectures used in integrated circuits. A special phase hold circuit provides a mechanism for clocking circuits undergoing dynamic tests, permitting the dynamic test to produce proper results when the integrated circuit under test is clocked with a high-speed distributed clock. The functional logic clock enable is pipelined to synchronize the functional mode clock with the test mode clock when the tester mode is switched.
摘要翻译：用于测试高速边界扫描实现中的路径延迟的方法和装置克服了在集成电路中使用的流水线高速时钟架构所施加的限制。特殊的相位保持电路提供了一种用于时钟电路进行动态测试的机制，当被测集成电路用高速分布时钟计时时，允许动态测试产生正确的结果。当切换测试仪模式时，功能逻辑时钟使能被流水线化，以将功能模式时钟与测试模式时钟同步。

2. 发明申请

US20050107970A1 Built in self test circuit for measuring total timing uncertainty in a digital data path 有权
标题翻译：内置自检电路，用于测量数字数据路径中的总时序不确定度
公开(公告)号：US20050107970A1
公开(公告)日：2005-05-19
申请号：US10712925
申请日：2003-11-13
申请人： Robert Franch , William Huott , Norman James , Phillip Restle , Timothy Skergan
发明人： Robert Franch , William Huott , Norman James , Phillip Restle , Timothy Skergan
IPC分类号： G01R31/317 , G01R31/3185 , G06F19/00
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
摘要翻译：用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。延迟线抽头（逆变器输出）是由互补时钟对计时的寄存器的输入，以通过延迟线捕获启动时钟的进程，并识别出该进程中的任何变化（例如抖动，VDD噪声）。可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。

3. 发明申请

US20070236299A1 Measuring microprocessor susceptibility to internal noise generation 失效
公开(公告)号：US20070236299A1
公开(公告)日：2007-10-11
申请号：US11388002
申请日：2006-03-23
申请人： Sungjun Chun , Timothy Skergan , Ching Tong , Roger Weekly
发明人： Sungjun Chun , Timothy Skergan , Ching Tong , Roger Weekly
IPC分类号： H03B29/00
CPC分类号： G01R31/318378
摘要： A computer implemented method, testing system, computer usable program code, and apparatus are provided for measuring microprocessor susceptibility to internal noise A noise generator modulates a clock signal to generate noise on a targeted component within a microprocessor. A function generator executes microprocessor functions on a plurality of functional components within the microprocessor. A maximum execution frequency on the plurality of functional components is then measured and a set of frequency ranges where the functional components are susceptible to the generated noise is determined.

4. 发明申请

US20060179184A1 Method for providing low-level hardware access to in-band and out-of-band firmware 失效
标题翻译：用于提供对带内和带外固件的低级硬件访问的方法
公开(公告)号：US20060179184A1
公开(公告)日：2006-08-10
申请号：US11055675
申请日：2005-02-10
申请人： James Fields , Paul Lecocq , Brian Monwai , Thomas Pflueger , Kevin Reick , Timothy Skergan , Scott Swaney
发明人： James Fields , Paul Lecocq , Brian Monwai , Thomas Pflueger , Kevin Reick , Timothy Skergan , Scott Swaney
IPC分类号： G06F3/06 , G06F3/02 , G06F3/00
CPC分类号： G06F15/161
摘要： In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.
摘要翻译：带内固件执行指令，使指令在一致性结构上发送。 Fabric Snoop逻辑监视针对通过FSI链接附加的支持芯片之一的资源的命令包的一致性结构。转换逻辑将信息从Fabric数据包转换为FSI协议。 FSI命令通过FSI传输链路发送到预期支持芯片的FSI从站。 FSI接收链路从预期的支持芯片的FSI从站接收响应数据。转换逻辑将从通过FSI接收链路接收的支持芯片的信息转换为结构协议。响应分组生成逻辑生成结构响应分组并将其返回到一致性结构上。支持处理器和支持芯片之间的相同FSI链路允许通过带外固件直接访问支持芯片上的相同资源。

5. 发明申请

US20060176897A1 Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor 失效
标题翻译：用于间接访问内存映射资源的支持接口以减少带外支持处理器的系统连接的方法
公开(公告)号：US20060176897A1
公开(公告)日：2006-08-10
申请号：US11055404
申请日：2005-02-10
申请人： James Fields , Paul Lecocq , Brian Monwai , Thomas Pflueger , Kevin Reick , Timothy Skergan , Scott Swaney
发明人： James Fields , Paul Lecocq , Brian Monwai , Thomas Pflueger , Kevin Reick , Timothy Skergan , Scott Swaney
IPC分类号： H04L12/66
CPC分类号： G06F15/7842
摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.
摘要翻译：提供了一种用于存储器映射资源的支持接口的方法和装置。支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。内存映射支持接口更新内存，内存映射寄存器或内存映射资源。该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 Fabric命令转换为FSI协议，并转发到附加的支持芯片以访问内存映射资源，并将来自支持芯片的响应转换回Fabric响应数据包。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。系统还报告遇到的任何错误。

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