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1. 发明申请

US20050107970A1 Built in self test circuit for measuring total timing uncertainty in a digital data path 有权
标题翻译：内置自检电路，用于测量数字数据路径中的总时序不确定度
公开(公告)号：US20050107970A1
公开(公告)日：2005-05-19
申请号：US10712925
申请日：2003-11-13
申请人： Robert Franch , William Huott , Norman James , Phillip Restle , Timothy Skergan
发明人： Robert Franch , William Huott , Norman James , Phillip Restle , Timothy Skergan
IPC分类号： G01R31/317 , G01R31/3185 , G06F19/00
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
摘要翻译：用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。延迟线抽头（逆变器输出）是由互补时钟对计时的寄存器的输入，以通过延迟线捕获启动时钟的进程，并识别出该进程中的任何变化（例如抖动，VDD噪声）。可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。

2. 发明申请

US20060195737A1 System and method for characterization of certain operating characteristics of devices 审中-公开
标题翻译：用于表征设备某些操作特性的系统和方法
公开(公告)号：US20060195737A1
公开(公告)日：2006-08-31
申请号：US11055856
申请日：2005-02-11
申请人： Norman James
发明人： Norman James
IPC分类号： G01R31/28
CPC分类号： G01R31/31858
摘要： A system and method is provided for improving integrated circuit device characterization without requiring external tester hardware. On-chip circuitry is provided to measure the delay of a signal through a given scan chain when the scan chain latches have been placed in flush mode. A control signal generated by the on-chip circuitry simultaneously generates a timing measurement signal as well as initiates a counter/timer to count/time the amount of time it takes for the timing measurement signal to pass through certain operational circuitry of the integrated circuit device. The resolution of the measurement is the resolution of the integrated circuit device's global clock.
摘要翻译：提供了一种用于改进集成电路器件表征而不需要外部测试仪硬件的系统和方法。当扫描链锁定器处于冲洗模式时，提供片内电路以测量通过给定扫描链的信号的延迟。由片上电路产生的控制信号同时产生定时测量信号，并且启动计数器/定时器来对定时测量信号通过集成电路器件的某些操作电路所花费的时间量进行计数/计时。测量的分辨率是集成电路设备的全局时钟的分辨率。

3. 发明申请

US20060181337A1 Digitally tunable high-current current reference with high PSRR 失效
标题翻译：数字可调高电流电流参考，高PSRR
公开(公告)号：US20060181337A1
公开(公告)日：2006-08-17
申请号：US11055840
申请日：2005-02-11
申请人： Daniel Dreps , Norman James , Hector Saenz
发明人： Daniel Dreps , Norman James , Hector Saenz
IPC分类号： G05F1/10
CPC分类号： G05F1/46
摘要： A digitally tunable low voltage CMOS current reference is disclosed. A tunable current reference circuit is provided that includes a current source circuit that is coupled to a power supply voltage. The current source circuit provides a stable current reference output regardless of fluctuations in the power supply voltage. Multiple digitally selectable inputs are included in the current reference circuit and are coupled to the current source circuit. These inputs are used to adjust a value of the current reference output.
摘要翻译：公开了一种数字可调低电压CMOS电流参考。提供了一种可调谐电流参考电路，其包括耦合到电源电压的电流源电路。电流源电路提供稳定的电流参考输出，而不管电源电压的波动。多个数字可选输入包括在当前参考电路中并耦合到电流源电路。这些输入用于调整当前参考输出的值。

4. 发明申请

US20060022695A1 Defect monitor for semiconductor manufacturing capable of performing analog resistance measurements 失效
标题翻译：能够进行模拟电阻测量的半导体制造的缺陷监视器
公开(公告)号：US20060022695A1
公开(公告)日：2006-02-02
申请号：US10902668
申请日：2004-07-29
申请人： Arnold Barish , Norman James
发明人： Arnold Barish , Norman James
IPC分类号： G01R31/26
CPC分类号： G01R31/024
摘要： A mechanism is provided to address a structure under test and to identify a point of failure. A test open line carries a signal that indicates whether a structure under test is open or closed. A test short line carries a signal that indicates whether a structure under test is shorted. A test structure may include an array of cells, where each cell includes a circuit including structures to test. The cells may be scanned using scan only latches and signals on the test open and/or test short lines may be recorded. A test circuit may include a digital mode and an analog mode. The digital mode provides an open or closed value. The analog mode includes a programmable load. The output of the analog mode provides a resistance value that is relative to the programmable load.
摘要翻译：提供了一种机制来解决被测结构并确定故障点。测试开路线带有一个信号，指示被测结构是打开还是关闭。测试短线携带一个信号，指示被测结构是否短路。测试结构可以包括单元阵列，其中每个单元包括包括要测试的结构的电路。可以使用仅扫描锁存器扫描单元，并且可以记录测试打开的信号和/或测试短线。测试电路可以包括数字模式和模拟模式。数字模式提供打开或关闭的值。模拟模式包括可编程负载。模拟模式的输出提供了相对于可编程负载的电阻值。

5. 发明申请

US20060181325A1 System and method for providing on-chip clock generation verification using an external clock 审中-公开
标题翻译：使用外部时钟提供片内时钟生成验证的系统和方法
公开(公告)号：US20060181325A1
公开(公告)日：2006-08-17
申请号：US11055824
申请日：2005-02-11
申请人： Norman James , Brian Monwai
发明人： Norman James , Brian Monwai
IPC分类号： G06F1/04
CPC分类号： G11C29/02 , G01R31/31727 , G11C7/22 , G11C7/222 , G11C29/023 , G11C29/50012
摘要： A system and method for performing functional verification of a device, and in particular a technique for performing phase-locked loop (PLL) functional verification by the device which contains the PLL circuitry. A relatively slow-speed external clock is provided to the device, and is used to generate control signals to a counter. PLL circuitry within the device generates a relatively high-speed master clock signal for use by the device. This master clock signal is coupled to a clock input of the counter, the counter having various control inputs that are used to selectively count clock pulses of the master clock. As the frequency of the external clock signal is known, and the master clock signal is generated from known PLL circuitry, it is possible to analyze the count value from the counter to determine whether the PLL circuitry used to generate the master clock is operating properly.
摘要翻译：用于执行设备的功能验证的系统和方法，特别是用于由包含PLL电路的设备进行锁相环（PLL）功能验证的技术。相对较慢的外部时钟提供给设备，并用于产生控制信号到计数器。器件内的PLL电路产生相对高速的主时钟信号供设备使用。该主时钟信号耦合到计数器的时钟输入端，该计数器具有用于选择性地对主时钟的时钟脉冲进行计数的各种控制输入。由于外部时钟信号的频率是已知的，并且主时钟信号是从已知的PLL电路产生的，所以可以从计数器分析计数值，以确定用于产生主时钟的PLL电路是否正常工作。

6. 发明申请

US20060119397A1 Apparatus and method for accurately tuning the speed of an integrated circuit 有权
公开(公告)号：US20060119397A1
公开(公告)日：2006-06-08
申请号：US11002548
申请日：2004-12-02
申请人： Frank Ferraiolo , James Fields , Norman James , Bradley McCredie
发明人： Frank Ferraiolo , James Fields , Norman James , Bradley McCredie
IPC分类号： G01R29/02
CPC分类号： G01R31/31725
摘要： An apparatus and method for accurately tuning the speed of an integrated circuit, i.e. a computer chip, using a built-in sense circuit and controller are provided. The sense circuit is provided in association with a monitored path. The sense circuit includes a variable delay element coupled to a controller. A data signal from the monitored path is provided to the sense circuit which adds an amount of delay as determined by the controller to the data signal. The delayed data signal and the original data signal are compared to determine if their values match. If they match, then the amount of delay added by the variable delay element is increased. If they do not match, then a previous amount of delay, prior to the mismatch, is output as the slack of the monitored path. The slack may then be used to tune the speed of the integrated circuit.

7. 发明授权

US6135274A Disposable toothbrush 失效
标题翻译：一次性牙刷
公开(公告)号：US6135274A
公开(公告)日：2000-10-24
申请号：US369294
申请日：1999-08-06
申请人： Norman James
发明人： Norman James
IPC分类号： A46B11/00 , B65D83/00
CPC分类号： A46B11/0003 , A46B2200/1066
摘要： A portable toothbrush assembly is provided in which a toothbrush and mouth care solution dispenser are sealed within an outer bag. The dispenser preferably is constantly oriented above the bristles of the toothbrush until use. While remaining sealed within the outer bag, the dispenser can be squeezed in order to rupture the dispenser and distribute mouth care solution over the bristles of the toothbrush. The outer bag can then be opened, exposing the toothbrush for use and then, if desired, disposal.
摘要翻译：提供了一种便携式牙刷组件，其中牙刷和口腔护理溶液分配器被密封在外袋内。分配器优选地始终定向在牙刷的刷毛上方直到使用。当保持密封在外袋内时，可以挤压分配器以便使分配器破裂并且将口腔护理溶液分布在牙刷的刷毛上。然后可以打开外袋，暴露牙刷以供使用，然后如果需要，进行处理。

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