专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07406632B2 Error reporting network in multiprocessor computer 有权
标题翻译：在多处理器计算机中报错网络错误
公开(公告)号：US07406632B2
公开(公告)日：2008-07-29
申请号：US10607517
申请日：2003-06-26
申请人： Charles Sealey , John Lynch , Mark Myers , Jason Lewis , Stacey Lloyd , Paul Kayfes
发明人： Charles Sealey , John Lynch , Mark Myers , Jason Lewis , Stacey Lloyd , Paul Kayfes
IPC分类号： G06F11/00
CPC分类号： G06F11/0724 , G06F11/0772
摘要： A high-performance, high-reliable backplane bus has a simple configuration and operation. An error reporting network (ERN) provides an inexpensive approach to collecting the error state of a whole system in a uniform and consistent way. The uniformity allows for simpler interface software and for standardized hardware handling of classes of errors. In a preferred embodiment, serial error registers are used, minimizing implementation cost and making the software interface to the serial registers much easier. Serial error information is transferred over a separate data path from the main parallel bus, decreasing the chance of the original error corrupting the error information. Each CPU is provided with a local copy of the entire body of error information. The redundancy minimizes the impact of a possible CPU failure and allows the CPUs to coordinate error recovery.
摘要翻译：高性能，高可靠性的背板总线具有简单的配置和操作。错误报告网络（ERN）提供了一种以统一和一致的方式收集整个系统的错误状态的廉价方法。均匀性允许更简单的界面软件和用于错误类别的标准化硬件处理。在优选实施例中，使用串行错误寄存器，使实现成本最小化，并使得与串行寄存器的软件接口更容易。串行错误信息通过单独的数据路径从主并行总线传输，从而减少原始错误破坏错误信息的机会。每个CPU都提供了整个错误信息的本地副本。冗余可以最大限度地减少可能的CPU故障的影响，并允许CPU协调错误恢复。

2. 发明授权

US5787095A Multiprocessor computer backlane bus 失效
标题翻译：多处理器计算机背板总线
公开(公告)号：US5787095A
公开(公告)日：1998-07-28
申请号：US823587
申请日：1997-03-25
申请人： Mark Myers , Stacey Lloyd , Richard Stout , Robert Takasumi , John Lynch
发明人： Mark Myers , Stacey Lloyd , Richard Stout , Robert Takasumi , John Lynch
IPC分类号： G06F13/364 , G06F13/40 , G06F15/40 , H04L1/00
CPC分类号： G06F13/4068 , G06F13/364
摘要： A computer bus includes a first original signal line, a second redundant signal line, circuitry connected to the first original signal line and the second redundant signal line for driving the first original signal line and the second redundant signal line so as to convey on each identical information, circuitry for receiving signals on the first original signal line and the second redundant signal line, and error checking circuitry for comparing the signals on the first original signal line and the second redundant signal line and for indicating an error if the signals differ. By providing redundant signals for each signal that cannot be check with parity (for example wired-OR signals), the potential for single undetected points of failure is eliminated. In accordance with another embodiment of the invention, a computer having multiple modules connected by a backplane bus.
摘要翻译：计算机总线包括第一原始信号线，第二冗余信号线，连接到第一原始信号线的电路和用于驱动第一原始信号线和第二冗余信号线的第二冗余信号线，以便在每个相同的信息，用于在第一原始信号线和第二冗余信号线上接收信号的电路，以及用于比较第一原始信号线和第二冗余信号线上的信号的差错检测电路，以及用于在信号不同时指示错误。通过为不能用奇偶校验检查的每个信号（例如，有线或等信号）提供冗余信号，消除了单个未检测到的故障点的可能性。根据本发明的另一实施例，具有通过背板总线连接的多个模块的计算机。

3. 发明授权

US5581713A Multiprocessor computer backplane bus in which bus transactions are classified into different classes for arbitration 失效
标题翻译：多处理器计算机背板总线，其中总线事务被分类为不同的类进行仲裁
公开(公告)号：US5581713A
公开(公告)日：1996-12-03
申请号：US559043
申请日：1995-11-15
申请人： Mark Myers , Stacey Lloyd , Richard Stout , Robert Takasumi , John Lynch
发明人： Mark Myers , Stacey Lloyd , Richard Stout , Robert Takasumi , John Lynch
IPC分类号： G06F13/364 , G06F13/40 , G06F13/36
CPC分类号： G06F13/4068 , G06F13/364
摘要： A computer having multiple modules connected by a backplane bus includes multiple competition signal lines and multiple class signal lines. Access to the backplane bus to engage in one or more of multiple types of bus transactions is arbitrated between the modules by classifying the bus transactions into different classes and, during each of a succession of competition cycles, when a module wants access to the backplane bus to engage in a particular type of bus transaction, asserting a class signal line corresponding to a class in which the particular type of bus transaction has been classified. Based on information presented on the class signal lines, it is determined which modules are or are not eligible to compete for access to the backplane bus. When a module is eligible to compete for access to the backplane bus, it drives an identification code associated with the module on the competition signal lines. Then, based on information presented on the competition signal lines, a module is granted access to the backplane bus.
摘要翻译：具有通过背板总线连接的多个模块的计算机包括多个竞争信号线和多个类信号线。通过将总线事务分类为不同的类别，并且在连续的竞赛周期中的每一个期间当模块想要访问背板总线时，通过对模块之间的一种或多种类型的总线事务的访问进行仲裁参与特定类型的总线事务，断言对应于特定类型的总线交易已被分类的类的类信号线。根据类信号线上提供的信息，确定哪些模块有资格竞争接入背板总线。当模块有资格竞争访问背板总线时，它会在竞争信号线上驱动与模块相关的识别码。然后，根据竞争信号线上提供的信息，允许模块访问背板总线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式