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    • 1. 发明授权
    • Multiprocessor computer backplane bus in which bus transactions are
classified into different classes for arbitration
    • 多处理器计算机背板总线,其中总线事务被分类为不同的类进行仲裁
    • US5581713A
    • 1996-12-03
    • US559043
    • 1995-11-15
    • Mark MyersStacey LloydRichard StoutRobert TakasumiJohn Lynch
    • Mark MyersStacey LloydRichard StoutRobert TakasumiJohn Lynch
    • G06F13/364G06F13/40G06F13/36
    • G06F13/4068G06F13/364
    • A computer having multiple modules connected by a backplane bus includes multiple competition signal lines and multiple class signal lines. Access to the backplane bus to engage in one or more of multiple types of bus transactions is arbitrated between the modules by classifying the bus transactions into different classes and, during each of a succession of competition cycles, when a module wants access to the backplane bus to engage in a particular type of bus transaction, asserting a class signal line corresponding to a class in which the particular type of bus transaction has been classified. Based on information presented on the class signal lines, it is determined which modules are or are not eligible to compete for access to the backplane bus. When a module is eligible to compete for access to the backplane bus, it drives an identification code associated with the module on the competition signal lines. Then, based on information presented on the competition signal lines, a module is granted access to the backplane bus.
    • 具有通过背板总线连接的多个模块的计算机包括多个竞争信号线和多个类信号线。 通过将总线事务分类为不同的类别,并且在连续的竞赛周期中的每一个期间当模块想要访问背板总线时,通过对模块之间的一种或多种类型的总线事务的访问进行仲裁 参与特定类型的总线事务,断言对应于特定类型的总线交易已被分类的类的类信号线。 根据类信号线上提供的信息,确定哪些模块有资格竞争接入背板总线。 当模块有资格竞争访问背板总线时,它会在竞争信号线上驱动与模块相关的识别码。 然后,根据竞争信号线上提供的信息,允许模块访问背板总线。
    • 3. 发明申请
    • METHODS OF ADMINISTERING INJECTABLES TO A JOINT WITH A NEEDLE-FREE INJECTION SYSTEM
    • 使用无针注射系统联合注射器的方法
    • US20080171968A1
    • 2008-07-17
    • US11682452
    • 2007-03-06
    • Richard StoutNicolas Duval
    • Richard StoutNicolas Duval
    • A61M5/30
    • A61B17/3472A61M5/30
    • A method of delivering an injectable to a joint region with a needle-free injection system having a chamber with a first end and a second end, an orifice of a pre-selected size in the first end, and a plunger mechanism for ejecting fluids from within the chamber, through the orifice, and onto a target site. When the chamber is filled with an injectable, the plunger mechanism is configured to eject a selected amount of the injectable onto the target site at a pre-determined rate. A skin site adjacent a joint is selected. The orifice is placed in an injection position relative to the skin site, whereby the skin site is the target site. The injectable is ejected onto the skin site with the plunger mechanism, whereby at least a portion of the injectable is delivered through the skin site to intradermal, subcutaneous, intramuscular, and/or intra-articular regions of the joint.
    • 一种用无针注射系统输送注射到接头区域的方法,所述无针注射系统具有具有第一端和第二端的腔室,在第一端中具有预选尺寸的孔口,以及用于从第一端口排出流体的柱塞机构 在室内,通过孔口,并到达目标位置。 当腔室注入可注射时,柱塞机构构造成以预定速率将选定量的可注射物喷射到靶部位上。 选择与关节相邻的皮肤部位。 孔口相对于皮肤部位置于注射位置,由此皮肤部位是靶部位。 可注射剂用柱塞机构喷射到皮肤部位上,由此至少一部分注射剂通过皮肤部位输送到关节的皮内,皮下,肌内和/或关节内的区域。
    • 6. 发明授权
    • Multiprocessor computer backlane bus
    • 多处理器计算机背板总线
    • US5787095A
    • 1998-07-28
    • US823587
    • 1997-03-25
    • Mark MyersStacey LloydRichard StoutRobert TakasumiJohn Lynch
    • Mark MyersStacey LloydRichard StoutRobert TakasumiJohn Lynch
    • G06F13/364G06F13/40G06F15/40H04L1/00
    • G06F13/4068G06F13/364
    • A computer bus includes a first original signal line, a second redundant signal line, circuitry connected to the first original signal line and the second redundant signal line for driving the first original signal line and the second redundant signal line so as to convey on each identical information, circuitry for receiving signals on the first original signal line and the second redundant signal line, and error checking circuitry for comparing the signals on the first original signal line and the second redundant signal line and for indicating an error if the signals differ. By providing redundant signals for each signal that cannot be check with parity (for example wired-OR signals), the potential for single undetected points of failure is eliminated. In accordance with another embodiment of the invention, a computer having multiple modules connected by a backplane bus.
    • 计算机总线包括第一原始信号线,第二冗余信号线,连接到第一原始信号线的电路和用于驱动第一原始信号线和第二冗余信号线的第二冗余信号线,以便在每个相同的 信息,用于在第一原始信号线和第二冗余信号线上接收信号的电路,以及用于比较第一原始信号线和第二冗余信号线上的信号的差错检测电路,以及用于在信号不同时指示错误。 通过为不能用奇偶校验检查的每个信号(例如,有线或等信号)提供冗余信号,消除了单个未检测到的故障点的可能性。 根据本发明的另一实施例,具有通过背板总线连接的多个模块的计算机。