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1. 发明申请

US20050055478A1 Proxy direct memory access 有权
标题翻译：代理直接内存访问
公开(公告)号：US20050055478A1
公开(公告)日：2005-03-10
申请号：US10655370
申请日：2003-09-04
申请人： Charles Johns , Peichun Liu , Thuong Truong , Asano Shigehiro , Takeshi Yamazaki
发明人： Charles Johns , Peichun Liu , Thuong Truong , Asano Shigehiro , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.
摘要翻译：提供了一种用于为第一处理器建立直接存储器访问的系统和方法。该系统包括第一处理器和本地存储器。本地存储器耦合到第一处理器。第一直接存储器存取控制器（DMAC）耦合到第一处理器和本地存储器。系统存储器与第一DMAC通信。第二处理器与第一DMAC通信，使得第二处理器设置第一DMAC来处理本地存储器和系统存储器之间的数据传输。当第一个DMAC完成处理数据传输时，第二个处理器中断。

2. 发明申请

US20060015652A1 Establishing command order in an out of order DMA command queue 失效
标题翻译：在命令行DMA命令队列中建立命令顺序
公开(公告)号：US20060015652A1
公开(公告)日：2006-01-19
申请号：US10891772
申请日：2004-07-15
申请人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F13/14
CPC分类号： G06F13/28
摘要： A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.
摘要翻译：提供了一种用于控制存储器访问的方法，装置和计算机程序。直接存储器访问（DMA）单元已经在许多总线架构中变得普遍。然而，管理有限的系统资源已成为多个DMA单元的挑战。为了管理生成的多个命令并保留依赖关系，使用命令中的嵌入式标志或障碍命令。这些操作然后可以控制执行命令的顺序，以便保留依赖性。

3. 发明申请

US20060026309A1 Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment 有权
标题翻译：非对称异构多处理器环境中的内存障碍原语
公开(公告)号：US20060026309A1
公开(公告)日：2006-02-02
申请号：US10902474
申请日：2004-07-29
申请人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.
摘要翻译：本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。接收到存储器屏障命令并接收存储器命令。内存命令是根据内存屏障命令执行的。基于内存障碍命令启动总线操作。基于总线操作接收总线操作确认。基于总线操作确认执行存储器障碍命令。在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。

4. 发明申请

US20070079018A1 System and method for communicating command parameters between a processor and a memory flow controller 失效
标题翻译：用于在处理器和存储器流控制器之间传送命令参数的系统和方法
公开(公告)号：US20070079018A1
公开(公告)日：2007-04-05
申请号：US11207986
申请日：2005-08-19
申请人： Michael Day , Charles Johns , Peichun Liu , Todd Swanson , Thuong Truong
发明人： Michael Day , Charles Johns , Peichun Liu , Todd Swanson , Thuong Truong
IPC分类号： G06F13/00
CPC分类号： G06F13/32 , G06F13/1642
摘要： A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

5. 发明申请

US20050216610A1 Method to provide cache management commands for a DMA controller 失效
标题翻译：为DMA控制器提供高速缓存管理命令的方法
公开(公告)号：US20050216610A1
公开(公告)日：2005-09-29
申请号：US10809553
申请日：2004-03-25
申请人： Charles Johns , James Kahle , Peichun Liu , Thuong Truong
发明人： Charles Johns , James Kahle , Peichun Liu , Thuong Truong
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F13/28 , G06F12/0835 , G06F12/0837 , G06F12/0862
摘要： The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling the software program management of the caches. The commands include commands for writing data to the cache, loading data from the cache, and for marking data in the cache as no longer needed. The cache can be a system cache or a DMA cache.
摘要翻译：本发明提供了一种用于在支持DMA机制和高速缓存的系统中提供高速缓存管理命令的方法和系统。 DMA机制由处理器设置。处理器上运行的软件会生成缓存管理命令。 DMA机制执行命令，从而实现高速缓存的软件程序管理。这些命令包括用于将数据写入缓存的命令，从高速缓存加载数据，以及用于在不再需要的情况下将数据标记在缓存中。缓存可以是系统缓存或DMA高速缓存。

6. 发明申请

US20060149861A1 Methods and apparatus for list transfers using DMA transfers in a multi-processor system 有权
标题翻译：在多处理器系统中使用DMA传输的列表传输的方法和装置
公开(公告)号：US20060149861A1
公开(公告)日：2006-07-06
申请号：US11029891
申请日：2005-01-05
申请人： Takeshi Yamazaki , Tsutomu Horikawa , James Kahle , Charles Johns , Michael Day , Peichun Liu
发明人： Takeshi Yamazaki , Tsutomu Horikawa , James Kahle , Charles Johns , Michael Day , Peichun Liu
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , Y02D10/14
摘要： Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.
摘要翻译：方法和装置提供了响应于处理器向直接存储器访问控制器（DMAC）发出的单个DMA命令，在处理器的共享存储器和本地存储器之间传送多个数据块，其中处理器能够操作与共享存储器和DMAC的通信可操作地耦合到本地存储器。

7. 发明申请

US20050055506A1 Pseudo-LRU for a locking cache 有权
标题翻译：锁定缓存的伪LRU
公开(公告)号：US20050055506A1
公开(公告)日：2005-03-10
申请号：US10655366
申请日：2003-09-04
申请人： Jonathan DeMent , Ronald Hall , Peichun Liu , Thuong Truong
发明人： Jonathan DeMent , Ronald Hall , Peichun Liu , Thuong Truong
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/126 , G06F12/125 , G06F12/127 , Y10S707/99945 , Y10S707/99948
摘要： The present invention provides for a cache-accessing system employing a binary tree with decision nodes. A cache comprising a plurality of sets is provided. A locking or streaming replacement strategy is employed for individual sets of the cache. A replacement management table is also provided. The replacement management table is employable for managing a replacement policy of information associated with the plurality of sets. A pseudo least recently used function is employed to determine the least recently used set of the cache, for such reasons as set replacement. An override signal line is also provided. The override signal is employable to enable an overwrite of a decision node of the binary tree. A value signal is also provided. The value signal is employable to overwrite the decision node of the binary tree.
摘要翻译：本发明提供一种采用具有决策节点的二叉树的高速缓存访问系统。提供包括多个集合的高速缓存。缓存的单独集合采用锁定或流式替换策略。还提供了更换管理表。替换管理表可用于管理与多个集合相关联的信息的替换策略。由于诸如设置替换的原因，采用伪最近最少使用的功能来确定最近使用的高速缓存集合。还提供超驰信号线。覆盖信号可用于实现二叉树的决策节点的覆盖。还提供了值信号。值信号可用于覆盖二叉树的判定节点。

8. 发明申请

US20060015689A1 Implementation and management of moveable buffers in cache system 审中-公开
标题翻译：缓存系统中可移动缓冲区的实现和管理
公开(公告)号：US20060015689A1
公开(公告)日：2006-01-19
申请号：US10891796
申请日：2004-07-15
申请人： Yasukichi Okawa , Roy Kim , Peichun Liu , Thuong Truong
发明人： Yasukichi Okawa , Roy Kim , Peichun Liu , Thuong Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/0831
摘要： The present invention provides parallel processing of write-back and reload operations in a cache system and optimum circuit utilisation by implementing moveable buffers in a cache storage. However, the data and associated pointers are not permanently assigned to a particular buffer—hence, the buffers can move logically around in the facility. Reload pointer is pointing to an empty entry so that retrieved data from the main memory or equal hierarchy cache on cache miss can be always be accommodated. Victim pointer is always pointing to a modified entry for the next candidate of write-back operation. Write-back operation is necessary with reload operation in order to make a free entry for further cache miss handling unless free entry exists. Because of these moveable pointers for reload buffer and victim buffer and integrated write-back buffer in the cache, intra cache data movement is not necessary which improves cache miss handling performance.
摘要翻译：本发明通过在高速缓存存储器中实现可移动缓冲器来提供缓存系统中的回写和重新加载操作的并行处理以及最佳的电路利用。然而，数据和相关联的指针不会永久分配给特定的缓冲区，因此缓冲区可以在设备中逻辑移动。重新加载指针指向一个空条目，以便始终可以容纳来自主存储器或高速缓存未命中的等分层缓存的检索数据。受害者指针总是指向下一个回写操作候选者的修改条目。为了进一步缓存未命中处理，进行空闲条目，除非有空条目存在，否则重写操作是必须的。由于这些用于缓存缓冲区和受影响缓冲区以及集成回写缓冲区的可移动指针，因此不需要内部缓存数据移动，这提高了缓存未命中处理性能。

9. 发明申请

US20070162640A1 Method and system for efficient context swapping 有权
标题翻译：用于有效上下文交换的方法和系统
公开(公告)号：US20070162640A1
公开(公告)日：2007-07-12
申请号：US11291735
申请日：2005-12-01
申请人： Charles Johns , Peichun Liu , Takashi Omizo
发明人： Charles Johns , Peichun Liu , Takashi Omizo
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.
摘要翻译：公开了用于有效地切换处理元件之间的上下文的系统和方法。这些系统和方法可将处理元件的上下文传送到存储位置。使用目标处理元件的DMA控制器，该存储位置的内容可以被传送到与目标处理元件相关联的另一存储位置。然后，该上下文可以从该存储位置恢复到目标处理元件中的适当位置，并且目标处理元件然后可以利用该传送的上下文开始处理。

10. 发明授权

US07590774B2 Method and system for efficient context swapping 有权
标题翻译：用于有效上下文交换的方法和系统
公开(公告)号：US07590774B2
公开(公告)日：2009-09-15
申请号：US11291735
申请日：2005-12-01
申请人： Charles Johns , Peichun Liu , Takashi Omizo
发明人： Charles Johns , Peichun Liu , Takashi Omizo
IPC分类号： G06F13/28 , G06F7/38 , G06F9/00
CPC分类号： G06F13/28
摘要： Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.
摘要翻译：公开了用于有效地切换处理元件之间的上下文的系统和方法。这些系统和方法可以将处理元件的上下文传送到存储位置。使用目标处理元件的DMA控制器，该存储位置的内容可以被传送到与目标处理元件相关联的另一存储位置。然后，该上下文可以从该存储位置恢复到目标处理元件中的适当位置，并且目标处理元件然后可以利用该传送的上下文开始处理。

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