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1. 发明授权

US08098519B2 Semiconductor phase change memory using multiple phase change layers 有权
公开(公告)号：US08098519B2
公开(公告)日：2012-01-17
申请号：US12764157
申请日：2010-04-21
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

2. 发明授权

US08462545B2 Semiconductor phase change memory using multiple phase change layers 有权
公开(公告)号：US08462545B2
公开(公告)日：2013-06-11
申请号：US13526686
申请日：2012-06-19
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

3. 发明申请

US20120081956A1 SEMICONDUCTOR PHAST CHANGE MEMORY USING MULTIPLE PHASE CHANGE LAYERS 有权
标题翻译：使用多个相位变化层的半导体相位变化记忆
公开(公告)号：US20120081956A1
公开(公告)日：2012-04-05
申请号：US13315374
申请日：2011-12-09
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
摘要翻译：根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。这可能会降低所得相变存储器的功耗。功耗的降低可以通过在编程体积之外形成很少或不混合的相变材料的不同层来实现。例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

4. 发明申请

US20100200829A1 Semiconductor Phase Change Memory Using Multiple Phase Change Layers 有权
标题翻译：使用多相变层的半导体相变存储器
公开(公告)号：US20100200829A1
公开(公告)日：2010-08-12
申请号：US12764157
申请日：2010-04-21
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： H01L45/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
摘要翻译：根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。这可能会降低所得相变存储器的功耗。功耗的降低可以通过在编程体积之外形成很少或不混合的不同的相变材料层来实现。例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

5. 发明授权

US07729162B2 Semiconductor phase change memory using multiple phase change layers 有权
标题翻译：半导体相变存储器使用多个相变层
公开(公告)号：US07729162B2
公开(公告)日：2010-06-01
申请号：US11973565
申请日：2007-10-09
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
摘要翻译：根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。这可能会降低所得相变存储器的功耗。功耗的降低可以通过在编程体积之外形成很少或不混合的相变材料的不同层来实现。例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

6. 发明申请

US20130270502A1 Semiconductor Phase Change Memory Using Face Center Cubic Crystalline Phase Change Material 有权
标题翻译：半导体相变存储器使用面中心立方晶相变材料
公开(公告)号：US20130270502A1
公开(公告)日：2013-10-17
申请号：US13910237
申请日：2013-06-05
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： H01L45/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. In one embodiment, a face centered cubic chalcogenide structure may be utilized.
摘要翻译：根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。这可能会降低所得相变存储器的功耗。功耗的降低可以通过在编程体积之外形成很少或不混合的相变材料的不同层来实现。在一个实施方案中，可以使用面心立方硫属元素化合物结构。

7. 发明授权

US06673700B2 Reduced area intersection between electrode and programming element 有权
标题翻译：电极与编程元件之间的减少交点
公开(公告)号：US06673700B2
公开(公告)日：2004-01-06
申请号：US09895020
申请日：2001-06-30
申请人： Charles H. Dennison , Guy C. Wicker , Tyler A. Lowrey , Stephen J. Hudgens , Chien Chiang , Daniel Xu
发明人： Charles H. Dennison , Guy C. Wicker , Tyler A. Lowrey , Stephen J. Hudgens , Chien Chiang , Daniel Xu
IPC分类号： H01L21326
CPC分类号： H01L27/2463 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method comprising forming a sacrificial layer over less than the entire portion of a contact area on a substrate, the sacrificial layer having a thickness defining an edge over the contact area, forming a spacer layer over the spacer, the spacer layer conforming to the shape of the first sacrificial layer such that the spacer layer comprises an edge portion over the contact area adjacent the first sacrificial layer edge, removing the sacrificial layer, while retaining the edge portion of the spacer layer over the contact area, forming a dielectric layer over the contact area, removing the edge portion, and forming a programmable material to the contact area formerly occupied by the edge portion. An apparatus comprising a volume of programmable material, a conductor, and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area at one end coupled to the volume of programmable material, wherein the contact area is less than the surface area at the one end.
摘要翻译：一种方法，包括在小于衬底上的接触区域的整个部分上形成牺牲层，所述牺牲层具有限定在所述接触区域上的边缘的厚度，在所述间隔物上形成间隔层，所述隔离层符合形状的第一牺牲层，使得间隔层包括邻近第一牺牲层边缘的接触区域上的边缘部分，去除牺牲层，同时将间隔物层的边缘部分保持在接触区域上方，形成介于第接触区域，去除边缘部分，并且将可编程材料形成到以前由边缘部分占据的接触区域。一种包括可编程材料体积，导体和设置在所述可编程材料体积与所述导体之间的电极的装置，所述电极在一端与所述可编程材料的体积相连接的接触区域，其中所述接触面积小于一端的表面积。

8. 发明授权

US08223538B2 Semiconductor phast change memory using multiple phase change layers 有权
标题翻译：半导体相变存储器使用多个相变层
公开(公告)号：US08223538B2
公开(公告)日：2012-07-17
申请号：US13315374
申请日：2011-12-09
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
摘要翻译：根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。这可能会降低所得相变存储器的功耗。功耗的降低可以通过在编程体积之外形成很少或不混合的相变材料的不同层来实现。例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

9. 发明申请

US20090091971A1 Semiconductor phase change memory using multiple phase change layers 有权
标题翻译：半导体相变存储器使用多个相变层
公开(公告)号：US20090091971A1
公开(公告)日：2009-04-09
申请号：US11973565
申请日：2007-10-09
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
摘要翻译：根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。这可能会降低所得相变存储器的功耗。功耗的降低可以通过在编程体积之外形成很少或不混合的相变材料的不同层来实现。例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

10. 发明申请

US20080177943A1 Method and system for using dynamic random access memory as cache memory 有权
标题翻译：使用动态随机存取存储器作为高速缓冲存储器的方法和系统
公开(公告)号：US20080177943A1
公开(公告)日：2008-07-24
申请号：US12069812
申请日：2008-02-12
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译：高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

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