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1. 发明授权

US08065572B2 At-speed scan testing of memory arrays 有权
标题翻译：存储器阵列的高速扫描测试
公开(公告)号：US08065572B2
公开(公告)日：2011-11-22
申请号：US12495158
申请日：2009-06-30
申请人： Thomas A. Ziaja , Murali Gala , Paul J. Dickinson , Karl P. Dahlgren , David L. Curwen , Oliver Caty , Steven C. Krow-Lucal , James C. Hunt , Poh-Joo Tan
发明人： Thomas A. Ziaja , Murali Gala , Paul J. Dickinson , Karl P. Dahlgren , David L. Curwen , Oliver Caty , Steven C. Krow-Lucal , James C. Hunt , Poh-Joo Tan
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/32 , G01R31/318541 , G11C29/50012 , G11C2029/3202
摘要： An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.
摘要翻译：一种被配置用于对存储器阵列进行高速扫描测试的集成电路。集成电路包括具有多个串联扫描元件的扫描链，其中多个扫描元件的子集被耦合以向存储器阵列提供信号。多个扫描元件的子集的每个扫描元件包括具有数据输入的触发器和耦合到存储器阵列的对应输入的数据输出，以及被配置为在操作模式下耦合数据路径的选择电路并且还被配置为以扫描模式耦合到数据输入中的一个扫描输入，数据输出和数据输出的补码。该子集的扫描元件支持与其耦合的存储器阵列的高速测试。

2. 发明申请

US20100332924A1 AT-SPEED SCAN TESTING OF MEMORY ARRAYS 有权
标题翻译：记忆阵列的速度扫描测试
公开(公告)号：US20100332924A1
公开(公告)日：2010-12-30
申请号：US12495158
申请日：2009-06-30
申请人： Thomas A. Ziaja , Murali Gala , Paul J. Dickinson , Karl P. Dahlgren , David L. Curwen , Oliver Caty , Steven C. Krow-Lucal , James C. Hunt , Poh-Joo Tan
发明人： Thomas A. Ziaja , Murali Gala , Paul J. Dickinson , Karl P. Dahlgren , David L. Curwen , Oliver Caty , Steven C. Krow-Lucal , James C. Hunt , Poh-Joo Tan
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/32 , G01R31/318541 , G11C29/50012 , G11C2029/3202
摘要： An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.
摘要翻译：一种被配置用于对存储器阵列进行高速扫描测试的集成电路。集成电路包括具有多个串联扫描元件的扫描链，其中多个扫描元件的子集被耦合以向存储器阵列提供信号。多个扫描元件的子集的每个扫描元件包括具有数据输入的触发器和耦合到存储器阵列的对应输入的数据输出，以及被配置为在操作模式下耦合数据路径的选择电路并且还被配置为以扫描模式耦合到数据输入中的一个扫描输入，数据输出和数据输出的补码。该子集的扫描元件支持与其耦合的存储器阵列的高速测试。

3. 发明申请

US20100281442A1 TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES 有权
标题翻译：确定电路间接性的技术
公开(公告)号：US20100281442A1
公开(公告)日：2010-11-04
申请号：US12432002
申请日：2009-04-29
申请人： Paul J. Dickinson , Venkatesh P. Gopinath , Karl P. Dahlgren , Liang-Chi Chen
发明人： Paul J. Dickinson , Venkatesh P. Gopinath , Karl P. Dahlgren , Liang-Chi Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/31835
摘要： Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit.
摘要翻译：描述了与设备一起使用的设备（例如计算机系统或电路测试器），方法和计算机程序产品（即，软件）的实施例。这些系统和过程可以用于统计学地表征集成电路中的子电路之间的相互依赖性（被称为“侵略者 - 受害者关系”）。特别地，当集成电路针对一组状态变化差矢量失效时，侵略者和受害者之间的统计关系由性能度量（例如时钟速度）的值确定。使用这些统计关系，选择状态变化差向量的最坏情况子组，例如最坏情况子组。该子组可用于准确测试集成电路。

4. 发明授权

US08099705B2 Technique for determining circuit interdependencies 有权
标题翻译：确定电路相互依赖性的技术
公开(公告)号：US08099705B2
公开(公告)日：2012-01-17
申请号：US12432002
申请日：2009-04-29
申请人： Paul J. Dickinson , Venkatesh P. Gopinath , Karl P. Dahlgren , Liang-Chi Chen
发明人： Paul J. Dickinson , Venkatesh P. Gopinath , Karl P. Dahlgren , Liang-Chi Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/31835
摘要： Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit.
摘要翻译：描述了与设备一起使用的设备（例如计算机系统或电路测试器），方法和计算机程序产品（即，软件）的实施例。这些系统和过程可以用于统计学地表征集成电路中的子电路之间的相互依赖性（被称为“侵略者 - 受害者关系”）。特别地，当集成电路针对一组状态变化差矢量失效时，侵略者和受害者之间的统计关系由性能度量（例如时钟速度）的值确定。使用这些统计关系，选择状态变化差向量的最坏情况子组，例如最坏情况子组。该子组可用于准确测试集成电路。

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