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1. 发明授权

US08099705B2 Technique for determining circuit interdependencies 有权
标题翻译：确定电路相互依赖性的技术
公开(公告)号：US08099705B2
公开(公告)日：2012-01-17
申请号：US12432002
申请日：2009-04-29
申请人： Paul J. Dickinson , Venkatesh P. Gopinath , Karl P. Dahlgren , Liang-Chi Chen
发明人： Paul J. Dickinson , Venkatesh P. Gopinath , Karl P. Dahlgren , Liang-Chi Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/31835
摘要： Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit.
摘要翻译：描述了与设备一起使用的设备（例如计算机系统或电路测试器），方法和计算机程序产品（即，软件）的实施例。这些系统和过程可以用于统计学地表征集成电路中的子电路之间的相互依赖性（被称为“侵略者 - 受害者关系”）。特别地，当集成电路针对一组状态变化差矢量失效时，侵略者和受害者之间的统计关系由性能度量（例如时钟速度）的值确定。使用这些统计关系，选择状态变化差向量的最坏情况子组，例如最坏情况子组。该子组可用于准确测试集成电路。

2. 发明申请

US20100281442A1 TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES 有权
标题翻译：确定电路间接性的技术
公开(公告)号：US20100281442A1
公开(公告)日：2010-11-04
申请号：US12432002
申请日：2009-04-29
申请人： Paul J. Dickinson , Venkatesh P. Gopinath , Karl P. Dahlgren , Liang-Chi Chen
发明人： Paul J. Dickinson , Venkatesh P. Gopinath , Karl P. Dahlgren , Liang-Chi Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/31835
摘要： Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit.
摘要翻译：描述了与设备一起使用的设备（例如计算机系统或电路测试器），方法和计算机程序产品（即，软件）的实施例。这些系统和过程可以用于统计学地表征集成电路中的子电路之间的相互依赖性（被称为“侵略者 - 受害者关系”）。特别地，当集成电路针对一组状态变化差矢量失效时，侵略者和受害者之间的统计关系由性能度量（例如时钟速度）的值确定。使用这些统计关系，选择状态变化差向量的最坏情况子组，例如最坏情况子组。该子组可用于准确测试集成电路。

3. 发明授权

US07679978B1 Scheme for screening weak memory cell 有权
标题翻译：弱记忆细胞筛选方案
公开(公告)号：US07679978B1
公开(公告)日：2010-03-16
申请号：US11827542
申请日：2007-07-11
申请人： Hua-Yu Su , Raymond A Heald , Wen-Jay Hsu , Paul J. Dickinson , Venkatesh P Gopinath , Lik T Cheng , Shih-Huey Wu
发明人： Hua-Yu Su , Raymond A Heald , Wen-Jay Hsu , Paul J. Dickinson , Venkatesh P Gopinath , Lik T Cheng , Shih-Huey Wu
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5006
摘要： A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced leakage adjustment control (ILAC). The LSDC includes a combination of PMOS transistors, NMOS transistors or both PMOS and NMOS transistors that are controlled by a plurality of stress inducing signals. The PMOS and/or NMOS transistors of the LSDC are coupled to a pair of complementary data lines. The complementary data lines are inputs to a sense amplifier and are outputs of a write driver. The ILAC controls the quantity of the leakage stress applied through the LSDC to the pair of complementary data lines. The ILAC further includes a leakage varying circuitry that is configured to adjust the leakage stress applied to the complementary data lines through the LSDC. The applied leakage stress is adjusted to establish a desired pass/fail threshold and to detect other process variations or defects so that the sense amplifier can be applied to detect the voltage differential during a read operation. The applied leakage stress can also be applied to write driver circuitry such that a write driver along with the applied stress provide enough voltage level to screen difficult-to-write cell from a easy-to-write cell during a write operation. The plurality of stress inducing signals are controlled such that the appropriate leakage stress may be applied to force a leakage to Vdd or Vss associated with the cell through the complementary data lines.
摘要翻译：用于筛选弱记忆单元的新颖方案包括耦合到泄漏应力递送电路（LSDC）的细胞，其又耦合到诱导的泄漏调节控制（ILAC）。 LSDC包括由多个应力诱导信号控制的PMOS晶体管，NMOS晶体管或PMOS和NMOS晶体管的组合。 LSDC的PMOS和/或NMOS晶体管耦合到一对补充数据线。互补数据线是对读出放大器的输入，并且是写入驱动器的输出。 ILAC控制通过LSDC施加到一对互补数据线的泄漏应力的数量。 ILAC还包括泄漏变化电路，其被配置为调节通过LSDC施加到互补数据线的泄漏应力。调整所施加的泄漏应力以建立期望的通过/失败阈值并检测其他过程变化或缺陷，使得可以应用读出放大器来在读取操作期间检测电压差。施加的泄漏应力也可以应用于写入驱动器电路，使得写入驱动器与所施加的应力一起提供足够的电压电平，以在写入操作期间从易于写入的单元屏蔽难以写入的单元。控制多个应力诱导信号，使得可以施加适当的泄漏应力，以通过互补数据线将泄漏强迫与小区相关联的Vdd或Vss。

4. 发明授权

US08065572B2 At-speed scan testing of memory arrays 有权
标题翻译：存储器阵列的高速扫描测试
公开(公告)号：US08065572B2
公开(公告)日：2011-11-22
申请号：US12495158
申请日：2009-06-30
申请人： Thomas A. Ziaja , Murali Gala , Paul J. Dickinson , Karl P. Dahlgren , David L. Curwen , Oliver Caty , Steven C. Krow-Lucal , James C. Hunt , Poh-Joo Tan
发明人： Thomas A. Ziaja , Murali Gala , Paul J. Dickinson , Karl P. Dahlgren , David L. Curwen , Oliver Caty , Steven C. Krow-Lucal , James C. Hunt , Poh-Joo Tan
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/32 , G01R31/318541 , G11C29/50012 , G11C2029/3202
摘要： An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.
摘要翻译：一种被配置用于对存储器阵列进行高速扫描测试的集成电路。集成电路包括具有多个串联扫描元件的扫描链，其中多个扫描元件的子集被耦合以向存储器阵列提供信号。多个扫描元件的子集的每个扫描元件包括具有数据输入的触发器和耦合到存储器阵列的对应输入的数据输出，以及被配置为在操作模式下耦合数据路径的选择电路并且还被配置为以扫描模式耦合到数据输入中的一个扫描输入，数据输出和数据输出的补码。该子集的扫描元件支持与其耦合的存储器阵列的高速测试。

5. 发明申请

US20100332924A1 AT-SPEED SCAN TESTING OF MEMORY ARRAYS 有权
标题翻译：记忆阵列的速度扫描测试
公开(公告)号：US20100332924A1
公开(公告)日：2010-12-30
申请号：US12495158
申请日：2009-06-30
申请人： Thomas A. Ziaja , Murali Gala , Paul J. Dickinson , Karl P. Dahlgren , David L. Curwen , Oliver Caty , Steven C. Krow-Lucal , James C. Hunt , Poh-Joo Tan
发明人： Thomas A. Ziaja , Murali Gala , Paul J. Dickinson , Karl P. Dahlgren , David L. Curwen , Oliver Caty , Steven C. Krow-Lucal , James C. Hunt , Poh-Joo Tan
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/32 , G01R31/318541 , G11C29/50012 , G11C2029/3202
摘要： An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.
摘要翻译：一种被配置用于对存储器阵列进行高速扫描测试的集成电路。集成电路包括具有多个串联扫描元件的扫描链，其中多个扫描元件的子集被耦合以向存储器阵列提供信号。多个扫描元件的子集的每个扫描元件包括具有数据输入的触发器和耦合到存储器阵列的对应输入的数据输出，以及被配置为在操作模式下耦合数据路径的选择电路并且还被配置为以扫描模式耦合到数据输入中的一个扫描输入，数据输出和数据输出的补码。该子集的扫描元件支持与其耦合的存储器阵列的高速测试。

6. 发明授权

US07779316B2 Method of testing memory array at operational speed using scan 有权
标题翻译：使用扫描以运行速度测试存储器阵列的方法
公开(公告)号：US07779316B2
公开(公告)日：2010-08-17
申请号：US11950578
申请日：2007-12-05
申请人： Ishwardutt Parulkar , Gaurav H. Agarwal , Krishna B. Rajan , Paul J. Dickinson
发明人： Ishwardutt Parulkar , Gaurav H. Agarwal , Krishna B. Rajan , Paul J. Dickinson
IPC分类号： G11C29/00
CPC分类号： G06F11/267 , G01R31/318533
摘要： A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.
摘要翻译：用于以功能（操作）速度测试芯片的方法和系统。芯片可以包括具有布置成逻辑功能元件的数字触发器和存储器阵列的集成电路。可以包括额外的触发器以输出到一个或多个其他触发器，以便以功能速度向触发器提供输入，使得接收触发器在下一个功能时钟脉冲下根据所接收的输入以功能速度执行，以便于以功能速度测试芯片。

7. 发明申请

US20090150729A1 METHOD OF TESTING MEMORY ARRAY AT OPERATIONAL SPEED USING SCAN 有权
标题翻译：使用扫描测试操作速度的存储器阵列的方法
公开(公告)号：US20090150729A1
公开(公告)日：2009-06-11
申请号：US11950578
申请日：2007-12-05
申请人： Ishwardutt Parulkar , Gaurav H. Agarwal , Krishna B. Rajan , Paul J. Dickinson
发明人： Ishwardutt Parulkar , Gaurav H. Agarwal , Krishna B. Rajan , Paul J. Dickinson
IPC分类号： G06F11/277 , G06F11/26
CPC分类号： G06F11/267 , G01R31/318533
摘要： A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.
摘要翻译：用于以功能（操作）速度测试芯片的方法和系统。芯片可以包括具有布置成逻辑功能元件的数字触发器和存储器阵列的集成电路。可以包括额外的触发器以输出到一个或多个其他触发器，以便以功能速度向触发器提供输入，使得接收触发器在下一个功能时钟脉冲下根据所接收的输入以功能速度执行，以便于以功能速度测试芯片。

8. 发明授权

US07009625B2 Method of displaying an image of device test data 有权
标题翻译：显示设备测试数据图像的方法
公开(公告)号：US07009625B2
公开(公告)日：2006-03-07
申请号：US10386861
申请日：2003-03-11
申请人： Paul J. Dickinson
发明人： Paul J. Dickinson
IPC分类号： G09G5/00 , G06T11/20 , G01R31/28
CPC分类号： G09G3/006 , G09G5/02 , G09G5/363 , G09G2340/12
摘要： A method of displaying an image of device test data includes receiving a first device test file and a second device test tile including a first plurality of bits and a second plurality of bits, respectively. The method may also include generating a first graphic image representative of the first device test file by depicting each of the first plurality of bits using a unique pixel of a display. The method may also include generating a second graphic image representative of the second device test file by depicting each of the second plurality of bits using a unique pixel of a display. Further, the method may include overlaying the second graphic image onto the first graphic image.
摘要翻译：显示设备测试数据的图像的方法包括分别接收第一设备测试文件和包括第一多个位和第二多个位的第二设备测试块。该方法还可以包括通过使用显示器的唯一像素描绘第一多个比特中的每一个来生成代表第一设备测试文件的第一图形图像。该方法还可以包括通过使用显示器的唯一像素描绘第二多个位中的每一个来生成代表第二设备测试文件的第二图形图像。此外，该方法可以包括将第二图形图像叠加到第一图形图像上。

9. 发明授权

US06507925B1 Spatial and temporal alignment of a scan dump for debug of scan-based designs 有权
标题翻译：用于基于扫描的设计的扫描转储的空间和时间对齐
公开(公告)号：US06507925B1
公开(公告)日：2003-01-14
申请号：US09574710
申请日：2000-05-18
申请人： Sridhar Narayanan , Amitava Majumdar , Paul J. Dickinson , Gregory S. Clausen , Cary Chin
发明人： Sridhar Narayanan , Amitava Majumdar , Paul J. Dickinson , Gregory S. Clausen , Cary Chin
IPC分类号： G01R3128
CPC分类号： G01R31/304 , G01R31/31705 , G01R31/318552 , G01R31/318566
摘要： A method for analyzing a scan dump assigns a first latch to a first value, compares the first latch output to the first value for spatial alignment. The method then assigns a second latch to either a second or third value. The second value corresponds to before an event. The third value corresponds to after an event and may be incremented with ongoing clock cycles.
摘要翻译：用于分析扫描转储的方法将第一锁存器分配给第一值，将第一锁存器输出与第一值进行比较以用于空间对准。然后该方法将第二个锁存器分配给第二个或第三个值。第二个值对应于一个事件之前。第三个值对应于一个事件之后，并且可以随着正在进行的时钟周期递增。

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