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1. 发明授权

US5546544A Arbiter with a direct signal path that is modifiable under priority-conflict control 失效
标题翻译：仲裁器具有在优先级冲突控制下可修改的直接信号路径
公开(公告)号：US5546544A
公开(公告)日：1996-08-13
申请号：US342685
申请日：1994-11-21
申请人： Charles E. Dike , Farrell L. Ostler
发明人： Charles E. Dike , Farrell L. Ostler
IPC分类号： G06F9/48 , G06F13/14 , G06F13/26 , G06F13/362 , G06F13/00
CPC分类号： G06F13/14
摘要： An arbiter provides at an output a priority signal that indicates which one of the input signals at an input has gained priority over all other ones. The arbiter comprises a signal processing path between the input and the output for determining the priority signal. The arbiter further comprises a control means coupled to the signal path for detecting (rare) conflicts among priority candidates. In response to the detected conflict, the control means generates control signals to modify the signal path. This conflict-solving part of the arbiter is located outside the signal path. Accordingly, a signal propagation delay in the path is largely independent of the number of input signals.
摘要翻译：仲裁器在输出端提供一个优先级信号，该优先信号指示输入端的输入信号中的哪一个已经比所有其他信号获得优先级。仲裁器包括用于确定优先级信号的输入和输出之间的信号处理路径。仲裁器还包括耦合到信号路径的控制装置，用于检测优先候选者之间的（罕见的）冲突。响应于检测到的冲突，控制装置产生控制信号以修改信号路径。仲裁者的这个冲突解决部分位于信号路径之外。因此，路径中的信号传播延迟很大程度上与输入信号的数量无关。

2. 发明授权

US5341052A Arbiter with test capability and associated testing method 失效
标题翻译：具有测试能力和相关测试方法的仲裁者
公开(公告)号：US5341052A
公开(公告)日：1994-08-23
申请号：US141462
申请日：1993-10-21
申请人： Charles E. Dike , Farrell L. Ostler
发明人： Charles E. Dike , Farrell L. Ostler
IPC分类号： G06F13/14 , G01R19/145 , H04Q3/00
CPC分类号： G06F13/14
摘要： An arbiter based on pairwise mutual exclusion produces an absolute priority signal (G) indicating that one of three or more requests (R.sub.1, R.sub.2, . . . R.sub.N) has gained absolute priority over all the other. At least one mutual-exclusion element (20.sub.1 or 20p) in the arbiter is designed so that its pairwise priority determination car be reversed in response to at least one externally originated test signal (T.sub.1, T.sub.2 or T.sub.M-1, T.sub.M). By doing so after the requests have been asserted in a specified order, a priority conflict can be generated among the requests in order to check the conflict-resolution capability of the arbiter.
摘要翻译：基于成对互斥的仲裁器产生指示三个或更多个请求（R1，R2，...，RN）之一已经获得绝对优先级的绝对优先级信号（G）。仲裁器中的至少一个互斥元件（201或20p）被设计成响应于至少一个外部产生的测试信号（T1，T2或TM-1，TM）来反转其成对优先级确定轿厢。通过在请求以指定的顺序被断言之后这样做，可以在请求之间生成优先级冲突，以便检查仲裁器的冲突解决能力。

3. 发明授权

US5604450A High speed bidirectional signaling scheme 失效
标题翻译：高速双向信令方案
公开(公告)号：US5604450A
公开(公告)日：1997-02-18
申请号：US508159
申请日：1995-07-27
申请人： Shekhar Borkar , Stephen R. Mooney , Charles E. Dike
发明人： Shekhar Borkar , Stephen R. Mooney , Charles E. Dike
IPC分类号： H03K5/02 , H03K19/0175 , H03K19/00
CPC分类号： H03K19/01759 , H03K5/026
摘要： In a computer system having multiple components, a bidirectional scheme which allows bidirectional data communications between components over a single wire without using termination resistors by placing two drivers from two corresponding processor cores on the same wire, and allowing simultaneous data transfer in two directions. This doubles the effective bandwidth per pin without requiring a modification to the clocking scheme of the system. The driver is impedance matched to the line, and used as the termination for the driver on the opposite end of the wire. This reduces the termination power, since no power is consumed when both drivers are in the same state. The bidirectional flow of data creates a ternary encoding, with a relatively simple decoding possible.
摘要翻译：在具有多个组件的计算机系统中，双向方案允许通过单个线路在组件之间进行双向数据通信而不使用终端电阻器，通过将来自两个对应的处理器核心的两个驱动器放置在相同的线路上，并允许在两个方向上同时进行数据传输。这可以使每个引脚的有效带宽增加一倍，而不需要修改系统的时钟方案。驱动器与线路阻抗匹配，并用作线缆另一端的驱动器终端。这降低了终端功率，因为当两个驱动器处于相同状态时都不消耗电力。数据的双向流创建三进制编码，可以使用相对简单的解码。

4. 发明申请

US20130257493A1 LATCH WITH A FEEDBACK CIRCUIT 有权
标题翻译：带反馈电路的锁扣
公开(公告)号：US20130257493A1
公开(公告)日：2013-10-03
申请号：US13436106
申请日：2012-03-30
申请人： Charles E. Dike , Mark E. Schuelein
发明人： Charles E. Dike , Mark E. Schuelein
IPC分类号： H03L7/06 , H03K3/00
CPC分类号： H03K3/00 , H03K3/0375 , H03K3/35606
摘要： An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the first terminal The feedback circuit may include electronic logic elements to determine if the storage circuit is in a metastable state. The feedback circuit may couple at least one of the first and second terminals to one of a voltage reference and a voltage source if determined that the storage circuit is in a metastable state.
摘要翻译：装置可以包括可以具有第一端子和第二端子并且可以具有两个交叉耦合的反相器的存储电路。该装置可以包括耦合到第一端子的反馈电路。反馈电路可以包括用于确定存储电路是否处于亚稳态的电子逻辑元件。如果确定存储电路处于亚稳态，则反馈电路可以将第一和第二端子中的至少一个耦合到电压参考电压和电压源中的一个。

5. 发明申请

US20100332574A1 Digital random number generator 有权
标题翻译：数字随机数发生器
公开(公告)号：US20100332574A1
公开(公告)日：2010-12-30
申请号：US12459142
申请日：2009-06-26
申请人： Howard C. Herbert , George W. Cox , Shay Gueron , Jesse Walker , Charles E. Dike , Stephen A. Fischer , Ernie Brickell , Martin G. Dixon , David Johnston , Gunendran Thuraisingham , Edward V. Gamsaragan , James S. Coke , Greg W. Piper
发明人： Howard C. Herbert , George W. Cox , Shay Gueron , Jesse Walker , Charles E. Dike , Stephen A. Fischer , Ernie Brickell , Martin G. Dixon , David Johnston , Gunendran Thuraisingham , Edward V. Gamsaragan , James S. Coke , Greg W. Piper
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F9/30007 , H04L9/0861
摘要： A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.
摘要翻译：提供了一种基于硬件的数字随机数发生器。数字随机数发生器是基于一组非确定性行为的随机行为随机数发生器。非确定性行为包括子单元之间的时间不同步，熵源“额外”比特，熵测量，自主确定性随机比特生成器重新获取和来自共享资源的消费。

6. 发明授权

US5434892A Throttling circuit for a data transfer system 失效
标题翻译：数据传输系统的调节电路
公开(公告)号：US5434892A
公开(公告)日：1995-07-18
申请号：US307502
申请日：1994-09-16
申请人： Charles E. Dike , Jerry G. Jex
发明人： Charles E. Dike , Jerry G. Jex
IPC分类号： G06F5/10 , G06F5/12 , G06F5/14 , H04L23/00
CPC分类号： G06F5/14 , G06F5/12 , G06F2205/126
摘要： A data transfer system includes a buffer for storing data to be transferred out of the buffer and a register circuit coupled to the buffer for receiving the data from the buffer. The buffer generates a first indication signal when the buffer is almost empty. The buffer generates a second indication signal when the buffer is empty. The register circuit generates a request signal to receive the data from the buffer. The data transfer system further includes a throttling circuit coupled to the buffer and the register circuit for throttling data transmission to the register circuit from the buffer when the buffer generates the first indication signal and for stopping data transmission to the register circuit from the buffer when the buffer generates the second indication signal. The throttling circuit receives the first and second indication signals and the request signal. The throttling circuit maintains maximized data transfer rate between the buffer and the register circuit while immediately stopping the data transfer between the buffer and register circuit when the buffer is empty.
摘要翻译：数据传送系统包括用于存储要从缓冲器传出的数据的缓冲器和耦合到缓冲器的寄存器电路，用于从缓冲器接收数据。当缓冲区几乎为空时，缓冲区产生第一指示信号。当缓冲区为空时，缓冲区产生第二指示信号。寄存器电路产生从缓冲器接收数据的请求信号。数据传送系统还包括耦合到缓冲器的节流电路和用于当缓冲器产生第一指示信号时从缓冲器节流数据传输到寄存器电路的寄存器电路，并且当缓冲器产生第一指示信号时停止数据从缓冲器发送到寄存器电路缓冲区产生第二指示信号。节流电路接收第一和第二指示信号和请求信号。节流电路在缓冲器和寄存器电路之间保持最大化的数据传输速率，同时当缓冲器为空时立即停止缓冲器和寄存器电路之间的数据传输。

7. 发明申请

US20090113084A1 Controlling transmission on an asynchronous bus 失效
公开(公告)号：US20090113084A1
公开(公告)日：2009-04-30
申请号：US11978339
申请日：2007-10-29
申请人： Charles E. Dike
发明人： Charles E. Dike
IPC分类号： G06F3/00
CPC分类号： G06F13/4213
摘要： In one embodiment, the present invention includes a bus controller including a mutual exclusion unit to receive a data transmission request from first and second agents and to select one of the agents for servicing based on which agent is the first to send the request, multiple selection units controlled by the mutual exclusion unit, and a two-phase register coupled to at least one of the selection units to transmit data from the selected agent. Other embodiments are described and claimed.

8. 发明授权

US06642763B2 Long setup flip-flop for improved synchronization capabilities 失效
公开(公告)号：US06642763B2
公开(公告)日：2003-11-04
申请号：US10034081
申请日：2001-12-19
申请人： Charles E. Dike
发明人： Charles E. Dike
IPC分类号： H03K3289
CPC分类号： H03K3/356113 , H03K3/0375 , H03K3/356139 , H03K3/35625
摘要： A device and method for improving the synchronization and metastability resolving capabilities of a flip flop. At least one master latch resolves a metastable condition of a received data signal thereby generating a stable data signal which is received and then displayed by a slave latch. Latches with superior metastability time resolution are configured in a master-slave relationship along with a novel clocking scheme whereby the clock signal supplied to the master latch is inverted as compared to that which is supplied to slave latch. As a result, the input data is latched on a falling edge of a clock signal and subsequently displayed on the rising edge of the clock signal providing at one half cycle for the input data to settle before passing out the data thereby allowing metastabilities to resolve during that period.

9. 发明授权

US06512406B1 Backgate biased synchronizing latch 失效
标题翻译：背栅偏置同步锁存器
公开(公告)号：US06512406B1
公开(公告)日：2003-01-28
申请号：US09465437
申请日：1999-12-16
申请人： Charles E. Dike
发明人： Charles E. Dike
IPC分类号： H03K312
CPC分类号： H03K3/0375 , H03K3/356121
摘要： An apparatus having a latch core, where the latch core has a plurality of devices and at least one of the devices has a back gate bias net. A bias voltage circuit is coupled to the back gate bias net. The apparatus may further comprise back to back inverters where each inverter output is coupled to the other inverter input. The inverters may further comprise a PFET transistor and an NFET transistor, where the PFET transistors have a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors having a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors and the PFET transistors having a back gate bias net. The bias voltage circuit may be further configured to apply a bias voltage when a metastability may occur. The bias voltage circuit may further comprise a NAND gate.
摘要翻译：一种具有锁芯的装置，其中所述锁芯具有多个装置，并且所述装置中的至少一个具有背栅偏置网。偏压电路耦合到背栅偏置网。该装置还可以包括背对背反相器，其中每个反相器输出耦合到另一个反相器输入。反相器还可以包括PFET晶体管和NFET晶体管，其中PFET晶体管具有背栅偏压网。反相器还可以包括PFET晶体管和NFET晶体管，NFET晶体管具有背栅偏压网。反相器还可以包括PFET晶体管和NFET晶体管，NFET晶体管和PFET晶体管具有背栅偏压网。偏置电压电路还可以被配置为当亚稳态可能发生时施加偏置电压。偏置电压电路还可以包括NAND门。

10. 发明授权

US5404540A Arbiter with a uniformly partitioned architecture 失效
标题翻译：仲裁器具有均匀分区的架构
公开(公告)号：US5404540A
公开(公告)日：1995-04-04
申请号：US107414
申请日：1993-08-16
申请人： Charles E. Dike
发明人： Charles E. Dike
IPC分类号： G06F9/48 , G06F13/14 , G06F13/362 , G06F13/00
CPC分类号： G06F13/14
摘要： A multiple-input arbiter first mutually correlates groups of input signals for identifying a particular group, which includes at least one input signal that is a candidate for gaining the overall priority. Thereupon the priority winner is determined in that particular group. Such a hierarchical processing lends itself to an architecture wherein the processing in groups is implemented by cascaded levels of uniform logic blocks. The decomposition in uniform logic blocks considerably simplifies the design of arbiters that process large numbers of input signals.
摘要翻译：多输入仲裁器首先相互关联用于识别特定组的输入信号组，该特定组包括至少一个输入信号，该输入信号是用于获得整体优先级的候选者。因此，该优先级优胜者在该特定组中确定。这种分级处理本身适用于其中组中的处理由级联级别的统一逻辑块来实现的架构。统一逻辑块中的分解显着简化了处理大量输入信号的仲裁器的设计。

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