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1. 发明授权

US5546544A Arbiter with a direct signal path that is modifiable under priority-conflict control 失效
标题翻译：仲裁器具有在优先级冲突控制下可修改的直接信号路径
公开(公告)号：US5546544A
公开(公告)日：1996-08-13
申请号：US342685
申请日：1994-11-21
申请人： Charles E. Dike , Farrell L. Ostler
发明人： Charles E. Dike , Farrell L. Ostler
IPC分类号： G06F9/48 , G06F13/14 , G06F13/26 , G06F13/362 , G06F13/00
CPC分类号： G06F13/14
摘要： An arbiter provides at an output a priority signal that indicates which one of the input signals at an input has gained priority over all other ones. The arbiter comprises a signal processing path between the input and the output for determining the priority signal. The arbiter further comprises a control means coupled to the signal path for detecting (rare) conflicts among priority candidates. In response to the detected conflict, the control means generates control signals to modify the signal path. This conflict-solving part of the arbiter is located outside the signal path. Accordingly, a signal propagation delay in the path is largely independent of the number of input signals.
摘要翻译：仲裁器在输出端提供一个优先级信号，该优先信号指示输入端的输入信号中的哪一个已经比所有其他信号获得优先级。仲裁器包括用于确定优先级信号的输入和输出之间的信号处理路径。仲裁器还包括耦合到信号路径的控制装置，用于检测优先候选者之间的（罕见的）冲突。响应于检测到的冲突，控制装置产生控制信号以修改信号路径。仲裁者的这个冲突解决部分位于信号路径之外。因此，路径中的信号传播延迟很大程度上与输入信号的数量无关。

2. 发明授权

US5341052A Arbiter with test capability and associated testing method 失效
标题翻译：具有测试能力和相关测试方法的仲裁者
公开(公告)号：US5341052A
公开(公告)日：1994-08-23
申请号：US141462
申请日：1993-10-21
申请人： Charles E. Dike , Farrell L. Ostler
发明人： Charles E. Dike , Farrell L. Ostler
IPC分类号： G06F13/14 , G01R19/145 , H04Q3/00
CPC分类号： G06F13/14
摘要： An arbiter based on pairwise mutual exclusion produces an absolute priority signal (G) indicating that one of three or more requests (R.sub.1, R.sub.2, . . . R.sub.N) has gained absolute priority over all the other. At least one mutual-exclusion element (20.sub.1 or 20p) in the arbiter is designed so that its pairwise priority determination car be reversed in response to at least one externally originated test signal (T.sub.1, T.sub.2 or T.sub.M-1, T.sub.M). By doing so after the requests have been asserted in a specified order, a priority conflict can be generated among the requests in order to check the conflict-resolution capability of the arbiter.
摘要翻译：基于成对互斥的仲裁器产生指示三个或更多个请求（R1，R2，...，RN）之一已经获得绝对优先级的绝对优先级信号（G）。仲裁器中的至少一个互斥元件（201或20p）被设计成响应于至少一个外部产生的测试信号（T1，T2或TM-1，TM）来反转其成对优先级确定轿厢。通过在请求以指定的顺序被断言之后这样做，可以在请求之间生成优先级冲突，以便检查仲裁器的冲突解决能力。

3. 发明授权

US5924124A Software programmable bus disable system 失效
标题翻译：软件可编程总线禁用系统
公开(公告)号：US5924124A
公开(公告)日：1999-07-13
申请号：US863266
申请日：1997-05-27
申请人： Santanu Roy , Farrell L. Ostler
发明人： Santanu Roy , Farrell L. Ostler
IPC分类号： G06F12/14 , G06F13/16 , G06F13/38 , G06F13/14
CPC分类号： G06F13/385 , G06F13/16 , G06F12/1433 , G06F12/1441
摘要： A microcontroller, which is configured in a certain mode, may generate signals that can cause malfunctions of the microcontroller or of other devices. For example, a prefetch cycle at an internal memory boundary may attempt to access external memory via a port when the port is connected to an I/O device. The system of the invention gates such signals and thus prevents possible damage to the microcontroller or peripheral device. In a preferred embodiment, a software programmable register is provided with one location dedicated to storing a bit. When that register bit is set, it prevents certain signals and address/data from appearing at the port and thus possibly causing harm to the microcontroller or a peripheral device connected to the port.
摘要翻译：配置在某种模式下的微控制器可能产生可能导致微控制器或其他设备故障的信号。例如，当端口连接到I / O设备时，内部存储器边界的预取周期可能尝试通过端口访问外部存储器。本发明的系统将这种信号锁定，从而防止对微控制器或外围设备的可能的损坏。在优选实施例中，软件可编程寄存器被提供有专用于存储位的一个位置。当该寄存器位置1时，它会阻止某些信号和地址/数据出现在端口，从而可能对连接到端口的微控制器或外围设备造成危害。

4. 发明授权

US06820193B1 Branch instructions with decoupled condition and address 有权
标题翻译：具有解耦状态和地址的分支指令
公开(公告)号：US06820193B1
公开(公告)日：2004-11-16
申请号：US09466405
申请日：1999-12-17
申请人： Farrell L. Ostler , Antoine Farid Dagher
发明人： Farrell L. Ostler , Antoine Farid Dagher
IPC分类号： G06F944
CPC分类号： G06F9/3804
摘要： A processor architecture supports the decoupling of parameters typically associated with branch/jump instructions. Jump instructions are provided that do not contain an explicit destination address and other jump instructions are provided that do not contain an explicit test condition. The processing system provides a “default” value to any control element in the processor that is not expressly controlled by a particular instruction. In the case of a branch or call instruction, the default destination-address provided to effect the branch or call is the destination-address provided by a prior instruction. Subsequent or alternative branch or call instructions branch to this same address until the default address is set to a different address. In like manner, in most cases, the default condition that is used to determine the result of a conditional test, such as a conditional branch, call, or return instruction, is the last condition specified in a prior instruction.
摘要翻译：处理器架构支持通常与分支/跳转指令相关联的参数的去耦。提供了不包含显式目标地址的跳转指令，并且提供了不包含显式测试条件的其他跳转指令。处理系统为处理器中未被特定指令明确控制的任何控制元件提供“默认值”。在分支或呼叫指令的情况下，为实现分支或呼叫提供的默认目标地址是由先前指令提供的目的地址。后续或替代的分支或呼叫指令分支到同一地址，直到默认地址设置为不同的地址。以类似的方式，在大多数情况下，用于确定条件测试的结果（如条件分支，调用或返回指令）的默认条件是先前指令中指定的最后一个条件。

5. 发明授权

US5619663A Computer instruction prefetch system 失效
标题翻译：计算机指令预取系统
公开(公告)号：US5619663A
公开(公告)日：1997-04-08
申请号：US308051
申请日：1994-09-16
申请人： Ori K. Mizrahi-Shalom , Farrell L. Ostler , Gregory K. Goodhue
发明人： Ori K. Mizrahi-Shalom , Farrell L. Ostler , Gregory K. Goodhue
IPC分类号： G06F9/38 , G06F12/02
CPC分类号： G06F9/3814 , G06F12/0215 , G06F9/3802
摘要： An instruction prefetch system for a digital processor, and in particular a microcontroller which includes the prefetch system and instruction queue normally provided as part of the instruction fetch unit, to which is added a second instruction prefetch buffer in the system, preferably in the bus interface unit which serves as the memory interface unit. This added prefetch buffer has storage for only a small number of bytes or words, and operates to supply prefetched instructions to the queue in the instruction fetch unit. However, it operates under the following constraint: it only prefetches within the boundaries of each small block of code memory and stalls when a block boundary is reached until a new address appears. This approach combines some cache and prefetch principles for a limited cost design.
摘要翻译：一种用于数字处理器的指令预取系统，特别是包括通常作为指令获取单元的一部分提供的预取系统和指令队列的微控制器，其中在系统中添加了第二指令预取缓冲器，优选地在总线接口作为存储器接口单元的单元。这个添加的预取缓冲区只有少量的字节或字存储，并且操作以在指令获取单元中向队列提供预取指令。然而，它在以下约束下操作：它仅在每个小块代码存储器的边界内预取，并且当达到块边界直到新的地址出现时停止。这种方法结合了有限成本设计的一些缓存和预取原则。

6. 发明授权

US5594913A High speed memory access system for a microcontroller with directly driven low order address bits 失效
标题翻译：具有直接驱动低位地址位的微控制器的高速存储器存取系统
公开(公告)号：US5594913A
公开(公告)日：1997-01-14
申请号：US308060
申请日：1994-09-16
申请人： Farrell L. Ostler , Gregory K. Goodhue , Ori K. Mizrahi-Shalom
发明人： Farrell L. Ostler , Gregory K. Goodhue , Ori K. Mizrahi-Shalom
IPC分类号： G06F9/32 , G06F12/02 , G06F13/16 , G11C8/00 , G06F12/00
CPC分类号： G11C8/00 , G06F12/0215
摘要： A microcontroller which directly drives a memory with low order address bits during a fetch operation. Driving the low order address bits directly while the high order bits are latched during an address/data multiplex on the same pins allows the latch enable cycle to be skipped during sequential fetches. A sequential address detector indicates when the latch enable cycle can be skipped.
摘要翻译：在提取操作期间直接驱动低位地址位的存储器的微控制器。在同一个引脚的地址/数据多路复用期间，直接驱动低位地址位，同时在地址/数据多路复用期间锁存高位位允许在顺序读取期间跳过锁存使能周期。顺序地址检测器指示何时可以跳过锁存使能周期。

7. 发明授权

US07827327B1 Circuit for and method of realigning data 有权
标题翻译：电路和数据重新对齐方法
公开(公告)号：US07827327B1
公开(公告)日：2010-11-02
申请号：US12137498
申请日：2008-06-11
申请人： Douglas E. Thorpe , Farrell L. Ostler
发明人： Douglas E. Thorpe , Farrell L. Ostler
IPC分类号： G06F3/00 , G06F13/00 , G06F13/12
CPC分类号： G06F13/4018
摘要： A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.
摘要翻译：描述了能够重新对准数据的电路。电路通常包括接收第一多个输入数据字节和第二多个输入数据字节的输入多路复用器; 耦合到输入多路复用器并控制来自输入多路复用器的数据字节输出的开关控制器; 延迟寄存器，其耦合到所述输入多路复用器并接收所述第一多个输入数据字节的预定字节; 以及耦合到输入多路复用器和延迟寄存器的输出多路复用器。输出多路复用器接收第一多个输入数据字节的预定字节和第二多个输入数据字节的预定字节。

8. 发明授权

US07398334B1 Circuit for and method of realigning data 有权
标题翻译：电路和数据重新对齐方法
公开(公告)号：US07398334B1
公开(公告)日：2008-07-08
申请号：US10800367
申请日：2004-03-12
申请人： Douglas E. Thorpe , Farrell L. Ostler
发明人： Douglas E. Thorpe , Farrell L. Ostler
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F13/4018
摘要： A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.
摘要翻译：描述了能够重新对准数据的电路。电路通常包括接收第一多个输入数据字节和第二多个输入数据字节的输入多路复用器; 耦合到输入多路复用器并控制来自输入多路复用器的数据字节输出的开关控制器; 延迟寄存器，其耦合到所述输入多路复用器并接收所述第一多个输入数据字节的预定字节; 以及耦合到输入多路复用器和延迟寄存器的输出多路复用器。输出多路复用器接收第一多个输入数据字节的预定字节和第二多个输入数据字节的预定字节。

9. 发明授权

US07032100B1 Simple algorithmic cryptography engine 有权
标题翻译：简单的算法加密引擎
公开(公告)号：US07032100B1
公开(公告)日：2006-04-18
申请号：US09466392
申请日：1999-12-17
申请人： George Samuel Fleming , Farrell L. Ostler , Antoine Farid Dagher
发明人： George Samuel Fleming , Farrell L. Ostler , Antoine Farid Dagher
IPC分类号： G06F12/00
CPC分类号： G06F9/30058 , G06F9/322
摘要： A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the device, thereby reducing the surface area required, and associated costs. A variety of techniques are also employed to ease the task of programming the processor for cryptographic processes, and to optimize the efficiency of instructions that are expected to be commonly used in the programming of such processes. In a preferred low-cost embodiment, a single-port random-access memory (RAM) is used for operand storage, few data busses and registers are used in the data-path, and the instruction set is optimized for parallel operations within instructions. Because cryptographic processes are characterized by operations on wide data items, particular emphasis is placed on the efficient processing of multi-word operations, including the use of constants having the same width as an instruction word. A simplified arithmetic unit is provided that efficiently supports the functions typically required for cryptographic operations with minimal overhead. A microcode-mapped instruction set is utilized in a preferred embodiment to facilitate multiple parallel operations in each instruction cycle and to provide direct processing control with minimal overhead.
摘要翻译：提供了特别适用于加密处理的处理器架构和指令集。使用各种技术来最小化设计的复杂性并且最小化设备内的互连的复杂性，从而减少所需的表面积以及相关的成本。还采用各种技术来简化用于加密处理器的编程任务，并且优化预期在这种处理的编程中常用的指令的效率。在优选的低成本实施例中，单端口随机存取存储器（RAM）用于操作数存储，在数据路径中使用很少的数据总线和寄存器，并且指令集优化用于指令内的并行操作。由于加密过程的特征在于对宽数据项的操作，特别强调多字操作的有效处理，包括使用与指令字宽度相同的常数。提供了一种简化的算术单元，可以以最小的开销高效地支持密码操作通常所需的功能。在优选实施例中使用微代码映射指令集以促进每个指令周期中的多个并行操作，并以最小的开销提供直接的处理控制。

10. 发明授权

US06782447B2 Circular address register 有权
标题翻译：循环地址寄存器
公开(公告)号：US06782447B2
公开(公告)日：2004-08-24
申请号：US09466404
申请日：1999-12-17
申请人： Farrell L. Ostler , Antoine Farid Dagher
发明人： Farrell L. Ostler , Antoine Farid Dagher
IPC分类号： G06F1206
CPC分类号： G06F7/5055 , G06F7/49931 , G06F9/3552 , G06F9/3879
摘要： A device and corresponding programming instructions are provided that facilitate a circular addressing process. The device is configured to provide an address output that is constrained to lie within specified bounds. When a “circular increment” or “circular decrement” instruction is executed that would cause the address to exceed a bound, the address is reset to the other bound. In a preferred embodiment, the programming instruction also sets condition flags that indicate when the address is at each bound. By providing these “bounds” flags in conjunction with the circular addressing operation, multiple-word data items can be processed efficiently. A base-address of N contiguous words in a memory is loaded into the circular register, and a circular addressing instruction is used to access each word of the N contiguous words in sequence; a bounds flag is set when the last word of the multi-word data item is accessed.
摘要翻译：提供了一种便于循环寻址过程的设备和相应的编程指令。该设备被配置为提供被限制在指定范围内的地址输出。当执行会导致地址超过限制的“循环增量”或“循环递减”指令时，地址将重置为另一个绑定。在优选实施例中，编程指令还设置指示何时在每个绑定处的地址的条件标志。通过结合循环寻址操作提供这些“边界”标志，可以有效地处理多个字的数据项。存储器中N个连续字的基址被加载到循环寄存器中，并且使用循环寻址指令来顺序地访问N个连续字的每个字; 当访问多字数据项的最后一个字时，设置边界标志。

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