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1. 发明授权

US5504903A Self-progamming of on-chip program memory for microcontroller at clock start-up 失效
标题翻译：在时钟启动时，用于微控制器的片上程序存储器的自动编程
公开(公告)号：US5504903A
公开(公告)日：1996-04-02
申请号：US192958
申请日：1994-02-07
申请人： Chao-Wu Chen , Kurt Rosenhagen , Greg Italiano , Sumit Mitra
发明人： Chao-Wu Chen , Kurt Rosenhagen , Greg Italiano , Sumit Mitra
IPC分类号： G06F9/24 , G06F9/445 , G06F9/06
CPC分类号： G06F9/24 , G06F9/445
摘要： A microcontroller fabricated on a semiconductor chip is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. A clock generates timing signals to control the timing of the microcontroller execution and operation. An on-chip program memory has space avilable for storing a program to be executed by the microcontroller in sequential steps in successive address locations of the program memory. An instruction stored in unerasable memory on the chip initiates self-programming of the program memory with the program to be executed by the microcontroller by enabling a pointer timed by the clock to alternately read addresses containing steps of the program to be executed from off-chip memories and to write same into successive addresses of the on-chip program memory by incrementing the latter addresses with each step to be written therein.
摘要翻译：制造在半导体芯片上的微控制器在操作时适于执行程序和指令，并且作为响应，适于产生控制信号以选择性地控制外部设备。时钟产生定时信号以控制微控制器执行和操作的时序。片上程序存储器具有可用于存储由微控制器在程序存储器的连续地址位置中的连续步骤执行的程序的空间。存储在芯片上的不可擦除存储器中的指令通过使由时钟指针定时的指针交替地读取包含要从芯片外执行的程序的步骤的地址，从而启动程序存储器的自编程，并由要由微控制器执行的程序存储器，并且通过用要在其中写入的每个步骤递增后一个地址，将其写入片上程序存储器的连续地址。

2. 发明授权

US06552567B1 Functional pathway configuration at a system/IC interface 失效
标题翻译：功能通道在系统/ IC接口配置
公开(公告)号：US06552567B1
公开(公告)日：2003-04-22
申请号：US09964664
申请日：2001-09-28
申请人： Brian Boles , Richard Fischer , Sumit Mitra , Rodney Drake , Stephen A. Bowling , Bryan Kris , Steven Marsh , Hassan Harb
发明人： Brian Boles , Richard Fischer , Sumit Mitra , Rodney Drake , Stephen A. Bowling , Bryan Kris , Steven Marsh , Hassan Harb
IPC分类号： H03K190175
CPC分类号： G06F15/76
摘要： The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.
摘要翻译：本发明一般涉及集成电路（IC）与IC连接的电路组件之间的接口上的功能通路配置。更具体地说，本发明一般涉及包括IC封装的一个或多个半导体集成电路管芯与系统的电路之间的界面处的功能通路配置，其中集成电路管芯是数字信号控制器。更具体地，本发明涉及用于数字信号控制器和嵌入其中的系统之间的接口的18,28,40,44,64或80引脚功能通路配置。

3. 发明授权

US5294928A A/D converter with zero power mode 失效
标题翻译：零功率模式的A / D转换器
公开(公告)号：US5294928A
公开(公告)日：1994-03-15
申请号：US938908
申请日：1992-08-31
申请人： Russ Cooper , Sumit Mitra
发明人： Russ Cooper , Sumit Mitra
IPC分类号： H03M1/00 , H03M1/46 , H03M1/80 , H03K3/01
CPC分类号： H03M1/002 , H03M1/468 , H03M1/804
摘要： A semiconductor microcontroller includes the capability to perform analog to digital conversions of an analog signal representative of a variable parameter indicative of the need to exercise a control function. While the analog to digital conversions are being performed, the microcontroller processor can be placed in a sleep mode which eliminates noise arising from switching activities of the processor as a source of inaccuracy in the conversion process. At the end of the conversion, the analog to digital converter can either shut itself down or wake up the processor. Alternatively, the converter may shut itself down in response to a different user selected control signal.
摘要翻译：半导体微控制器包括执行模拟信号的模数转换的能力，该模拟信号表示表示需要行使控制功能的可变参数。在执行模数转换的同时，微控制器处理器可以被置于睡眠模式，消除由于处理器的切换活动而产生的噪声，作为转换过程中的不准确之源。在转换结束时，模数转换器可以自动关闭或唤醒处理器。或者，转换器可以响应于不同的用户选择的控制信号而关闭自身。

4. 发明授权

US6029241A Processor architecture scheme having multiple bank address override sources for supplying address values and method therefor 失效
标题翻译：具有用于提供地址值的多个存储体地址覆盖源的处理器架构方案及其方法
公开(公告)号：US6029241A
公开(公告)日：2000-02-22
申请号：US959405
申请日：1997-10-28
申请人： Igor Wojewoda , Sumit Mitra , Rodney J. Drake
发明人： Igor Wojewoda , Sumit Mitra , Rodney J. Drake
IPC分类号： G06F9/34 , G06F9/30 , G06F9/35 , G06F12/06
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30138 , G06F9/35
摘要： A processor architecture scheme which allows for encoding multiple addressing modes and which has multiple sources for generating a bank address value. The processor architecture scheme has a Central Processing Unit (CPU) for executing an instruction set. A data memory is coupled to the CPU. The data memory is used for storing and transferring data to and from the CPU. The data memory is divided into a plurality of banks wherein one of the plurality of banks is a dedicated bank for general and special purpose registers. A selection circuit is coupled to the data memory. The selection circuit is used for selecting one of the multiple sources for generating the bank address value. A bank select register is coupled to the selection circuit. The bank select register is used for supplying a bank address value for an instruction to be executed in a direct short addressing mode. An instruction register is coupled to the selection circuit for supplying a bank address values for an instruction to be executed in a direct long addressing mode and for supplying a register address within a bank for the instruction to be executed in a direct short addressing mode.
摘要翻译：一种处理器架构方案，其允许对多个寻址模式进行编码，并且具有用于生成存储体地址值的多个源。处理器架构方案具有用于执行指令集的中央处理单元（CPU）。数据存储器耦合到CPU。数据存储器用于存储和传输数据到和从CPU传输数据。数据存储器被分成多个存储体，其中多个存储体中的一个存储体是用于通用和专用寄存器的专用库。选择电路耦合到数据存储器。选择电路用于选择多个源之一以产生存储体地址值。存储体选择寄存器耦合到选择电路。存储体选择寄存器用于提供要在直接短寻址模式下执行的指令的存储体地址值。指令寄存器耦合到选择电路，用于提供用于以直接长寻址模式执行的指令的存储体地址值，以及用于以直接短寻址模式提供要执行的指令的存储体内的寄存器地址。

5. 发明授权

US07206924B2 Microcontroller instruction set 有权
标题翻译：微控制器指令集
公开(公告)号：US07206924B2
公开(公告)日：2007-04-17
申请号：US10751210
申请日：2003-12-31
申请人： Edward Brian Boles , Rodney Drake , Darrel Johansen , Sumit Mitra , Joseph Triece , Randy Yach
发明人： Edward Brian Boles , Rodney Drake , Darrel Johansen , Sumit Mitra , Joseph Triece , Randy Yach
IPC分类号： G06F12/08
CPC分类号： G06F9/30192 , G06F9/30032 , G06F9/3004 , G06F9/30101 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/321 , G06F9/325
摘要： A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performances and decreasing program memory usage.
摘要翻译：微控制器装置设置有用于操纵微控制器的行为的指令集。提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。可以通过寄存器文件或数据存储器进行直接或间接寻址。特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。因此，在两个操作数指令中要使用两个文件寄存器。这允许在两个寄存器之间直接移动数据，而不经过W寄存器。从而增加性能并减少程序内存的使用。

6. 发明申请

US20050257016A1 Digital signal controller secure memory partitioning 审中-公开
标题翻译：数字信号控制器安全的内存分区
公开(公告)号：US20050257016A1
公开(公告)日：2005-11-17
申请号：US10846579
申请日：2004-05-17
申请人： Brian Boles , Sumit Mitra , Steven Marsh
发明人： Brian Boles , Sumit Mitra , Steven Marsh
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F12/1491
摘要： A controller offers various security modes for protecting program code and data stored in memory and ensuring that the protection is effective during all normal operating conditions of the controller. The controller includes configuration settings that segment program memory into a boot segment, a secure segment and a general segment, each with a particular level of security including no enhanced protection. The boot code segment (BS) is the most secure and may be used to store a secure boot loader. The secure code segment (SS) is useful for storing proprietary algorithms from third parties, such as algorithms for separating ambient noise from speech in speech recognition applications. The general code segment (GS) has the least security. The controller is configured to prevent program flow changes that would result in program code stored in high security segments from being accessed by program code stored in lower security segments. In addition, the processor may be configured to have associated secure data portions of both program memory, such as flash memory, and random access memory (RAM) corresponding to the BS, SS and GS. Attempts to read data from or write data to the program memory or RAM associated with a higher security level from a lower security level are prevented from occurring.
摘要翻译：控制器提供各种安全模式，用于保护存储在存储器中的程序代码和数据，并确保在控制器的所有正常操作条件下保护有效。控制器包括将程序存储器分割为引导段，安全段和通用段的配置设置，每个段具有特定级别的安全性，不包括增强的保护。启动代码段（BS）是最安全的，可用于存储安全引导加载程序。安全代码段（SS）用于存储来自第三方的专有算法，例如用于在语音识别应用中分离环境噪声与语音的算法。一般代码段（GS）的安全性最低。控制器被配置为防止程序流程改变，导致存储在高安全段中的程序代码被存储在较低安全段中的程序代码访问。此外，处理器可以被配置为具有诸如闪存之类的程序存储器和对应于BS，SS和GS的随机存取存储器（RAM）的相关联的安全数据部分。防止从较低安全级别读取数据或从与较高安全级别相关联的程序存储器或RAM写入数据的尝试发生。

7. 发明授权

US5473758A System having input output pins shifting between programming mode and normal mode to program memory without dedicating input output pins for programming mode 失效
标题翻译：具有输入输出引脚在编程模式和正常模式之间切换到程序存储器的系统，而不用将输入输出引脚用于编程模式
公开(公告)号：US5473758A
公开(公告)日：1995-12-05
申请号：US938911
申请日：1992-08-31
申请人： Ray Allen , Sumit Mitra , Rodney Drake
发明人： Ray Allen , Sumit Mitra , Rodney Drake
IPC分类号： G11C16/10 , G06F15/02
CPC分类号： G11C16/102
摘要： A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The microcontroller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit programming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.
摘要翻译：在单个半导体芯片中制造微控制器和相关联的EPROM程序存储器。微控制器设备适于在使用要由设备控制的系统安装设备的电路中的数字命令字或其他位模式中使用数字命令字或其他位模式进行编程，并将其编程引脚与系统隔离以避免对系统运行时正在进行编程。在线编程使用量远低于设备的输入/输出（I / O）引脚总数，总共少于命令字中的位数。这是通过引脚和程序存储器之间的串行/并行编程接口实现的，并且通过将数据以串行方式应用于其被锁存并且并行加载到存储器中的接口来实现。输入到设备的数据可以替代地以与字节相同的字节并行输入，该字节的宽度小于设备的I / O引脚的总数。

8. 发明申请

US20060187106A1 Analog-to-digital converter with interchangeable resolution and sample and hold amplifier channels 有权
标题翻译：具有可互换分辨率和采样和保持放大器通道的模数转换器
公开(公告)号：US20060187106A1
公开(公告)日：2006-08-24
申请号：US11358289
申请日：2006-02-21
申请人： Sumit Mitra , Harry Hu , Pieter Schieke
发明人： Sumit Mitra , Harry Hu , Pieter Schieke
IPC分类号： H03M1/12
CPC分类号： H03M1/004 , H03M1/007 , H03M1/1225 , H03M1/468 , H03M1/68 , H03M1/804
摘要： A successive approximation register analog-to-digital converter (SAR ADC) having a sample, hold and convert amplifier circuit may be configured for either a single channel SAR ADC or a multiple channel SAR ADC. Switches or metal connection options, e.g., bit configurable or metal mask configurable, respectively, may be used to configure a common capacitor area, a portion of which may be used as a reconfigurable charge-redistribution digital-to-analog converter (CDAC) of the SAR ADC as either a single channel sample, hold and convert 12-bit capacitor configuration or a four channel sample, hold and convert 10-bit capacitor configuration. All other parts of the SAR ADC circuitry may be substantially the same for either configuration, e.g., the resistive digital-to-analog converter (RDAC), successive approximation register (SAR), ADC controller, sample, hold and convert switches, comparator, etc, may be substantially the same for either the single or multiple channel SAR ADC configurations.
摘要翻译：具有采样，保持和转换放大器电路的逐次逼近寄存器模数转换器（SAR ADC）可以配置为单通道SAR ADC或多通道SAR ADC。可以分别使用开关或金属连接选项，例如位配置或金属掩模可配置，以配置公共电容器区域，其一部分可用作可重新配置的电荷再分配数模转换器（CDAC） SAR ADC作为单通道采样，保持和转换12位电容配置或四通道采样，保持和转换10位电容配置。 SAR ADC电路的所有其他部分对于任一配置可能基本相同，例如电阻数模转换器（RDAC），逐次逼近寄存器（SAR），ADC控制器，采样，保持和转换开关，比较器，对于单通道或多通道SAR ADC配置可能基本相同。

9. 发明授权

US06708268B1 Microcontroller instruction set 有权
标题翻译：微控制器指令集
公开(公告)号：US06708268B1
公开(公告)日：2004-03-16
申请号：US09280112
申请日：1999-03-26
申请人： Edward Brian Boles , Rodney Drake , Darrel Johansen , Sumit Mitra , Joseph Triece , Randy Yach
发明人： Edward Brian Boles , Rodney Drake , Darrel Johansen , Sumit Mitra , Joseph Triece , Randy Yach
IPC分类号： G06F1208
CPC分类号： G06F9/30192 , G06F9/30032 , G06F9/3004 , G06F9/30101 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/321 , G06F9/325
摘要： A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.
摘要翻译：微控制器装置设置有用于操纵微控制器的行为的指令集。提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。可以通过寄存器文件或数据存储器进行直接或间接寻址。特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。因此，在两个操作数指令中要使用两个文件寄存器。这允许在两个寄存器之间直接移动数据，而不经过W寄存器。从而提高性能并减少程序内存的使用。

10. 发明授权

US5454114A Microcontroller power-up delay 失效
标题翻译：微控制器上电延迟
公开(公告)号：US5454114A
公开(公告)日：1995-09-26
申请号：US238121
申请日：1994-04-04
申请人： Randy L. Yach , Sumit Mitra
发明人： Randy L. Yach , Sumit Mitra
IPC分类号： G06F1/04 , G06F1/24 , G06F11/267 , G06F15/78 , H03K17/22
CPC分类号： G06F1/24 , G06F11/221
摘要： A microcontroller is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller includes a power supply for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The microcontroller is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply is in a predetermined range and the clock frequency supplied by the clock is stable. In this way, no execution by the microcontroller is permitted until device stability is achieved, to prevent errors in execution. In the disclosed embodiment, the reset condition is maintained by a power-up timer and an oscillator start-up timer, each timer having a programmable timeout interval to end the reset condition only when the timeout intervals of both timers have expired.
摘要翻译：微控制器在操作时被调整为执行程序和指令，并且作为响应，适于产生控制信号以选择性地控制外部设备。微控制器包括用于在适合于其操作的预定范围内向总体设备供电的电源，以及用于以适于在设备内精确定时和计数的稳定性向微控制器提供时钟频率的时钟。微控制器被选择性地复位以防止其执行用于产生控制信号的程序和指令，并且尽管开始从复位状态移除直到电源提供的电源处于预定的状态时钟提供的时钟频率稳定。以这种方式，在实现器件稳定性之前，不允许微控制器的执行，以防止执行中的错误。在所公开的实施例中，复位条件由加电定时器和振荡器启动定时器维持，每个定时器具有可编程的超时间隔，以仅在两个定时器的超时间隔已经期满时才结束复位条件。

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