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1. 发明申请

US20070210341A1 Periphery design for charge balance power devices 有权
标题翻译：电荷平衡功率器件的周边设计
公开(公告)号：US20070210341A1
公开(公告)日：2007-09-13
申请号：US11375683
申请日：2006-03-13
申请人： Chanho Park , Joseph Yedinak , Christopher Kocon , Jason Higgs , Jaegil Lee
发明人： Chanho Park , Joseph Yedinak , Christopher Kocon , Jason Higgs , Jaegil Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/0634 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.
摘要翻译：电荷平衡半导体功率器件包括有源区，其具有p柱的条带和以交替方式布置的n个柱的条带，沿着有源区的长度延伸的p和n柱的条带。非活动周边区域包围有源区域，并且包括围绕有源区域的至少一个p环。最后一根直立在有源区域边缘上的p柱条的一端终止于大致直线，其中p柱的每条剩余的条的一端也结束。直线垂直于有源区域的长度延伸，n和p柱的条带沿着该区域的长度延伸。

2. 发明授权

US07595542B2 Periphery design for charge balance power devices 有权
标题翻译：电荷平衡功率器件的周边设计
公开(公告)号：US07595542B2
公开(公告)日：2009-09-29
申请号：US11375683
申请日：2006-03-13
申请人： Chanho Park , Joseph A. Yedinak , Christopher Boguslaw Kocon , Jason Higgs , Jaegil Lee
发明人： Chanho Park , Joseph A. Yedinak , Christopher Boguslaw Kocon , Jason Higgs , Jaegil Lee
IPC分类号： H01L29/93
CPC分类号： H01L29/0634 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.
摘要翻译：电荷平衡半导体功率器件包括有源区，其具有p柱的条带和以交替方式布置的n个柱的条带，沿着有源区的长度延伸的p和n柱的条带。非活动周边区域包围有源区域，并且包括围绕有源区域的至少一个p环。最后一根直立在有源区域边缘上的p柱条的一端终止于大致直线，其中p柱的每条剩余的条的一端也结束。直线垂直于有源区域的长度延伸，n和p柱的条带沿着该区域的长度延伸。

3. 发明授权

US07504691B2 Power trench MOSFETs having SiGe/Si channel structure 有权
标题翻译：具有SiGe / Si沟道结构的功率沟槽MOSFET
公开(公告)号：US07504691B2
公开(公告)日：2009-03-17
申请号：US11469456
申请日：2006-08-31
申请人： Chanho Park , Qi Wang
发明人： Chanho Park , Qi Wang
IPC分类号： H01L31/00
CPC分类号： H01L29/7813 , H01L29/1054 , H01L29/165 , H01L29/49 , H01L29/4933 , H01L29/66734 , H01L29/7782 , Y02P70/605
摘要： Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Other device characteristics are also improved. For example, parasitic gate impedance can reduced through the use of a poly SiGe gate. Also, channel resistance can be reduced through the use of a SiGe layer near the device's gate and a thick oxide region can be formed under the trench gate to reduce gate-to-drain capacitance.
摘要翻译：提高对瞬态电压的抗扰度并减少寄生阻抗的器件，方法和过程。提高对松开感应开关事件的抗扰度。例如，提供了具有SiGe源的沟槽门控功率MOSFET器件，其中SiGe源通过减少主体或阱区中的空穴电流来降低寄生npn晶体管增益，从而降低闩锁状态的可能性。还提供了具有SiGe体或阱区的沟槽栅功率MOSFET器件。当体二极管导通时，SiGe体减小空穴电流，从而降低反向恢复功率损耗。其他装置特性也得到改善。例如，通过使用多晶SiGe栅极可以减小寄生栅极阻抗。此外，可以通过在器件栅极附近使用SiGe层来减小沟道电阻，并且可以在沟槽栅极下形成厚的氧化物区域以减小栅极 - 漏极电容。

4. 发明申请

US20060289916A1 Power Trench MOSFETs Having SiGe/Si Channel Structure 有权
标题翻译：具有SiGe / Si通道结构的功率沟槽MOSFET
公开(公告)号：US20060289916A1
公开(公告)日：2006-12-28
申请号：US11469456
申请日：2006-08-31
申请人： Chanho Park , Qi Wang
发明人： Chanho Park , Qi Wang
IPC分类号： H01L27/108 , H01L31/00
CPC分类号： H01L29/7813 , H01L29/1054 , H01L29/165 , H01L29/49 , H01L29/4933 , H01L29/66734 , H01L29/7782 , Y02P70/605
摘要： Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Other device characteristics are also improved. For example, parasitic gate impedance can reduced through the use of a poly SiGe gate. Also, channel resistance can be reduced through the use of a SiGe layer near the device's gate and a thick oxide region can be formed under the trench gate to reduce gate-to-drain capacitance.
摘要翻译：提高对瞬态电压的抗扰度并减少寄生阻抗的器件，方法和过程。提高对松开感应开关事件的抗扰度。例如，提供了具有SiGe源的沟槽门控功率MOSFET器件，其中SiGe源通过减少主体或阱区中的空穴电流来降低寄生npn晶体管增益，从而降低闩锁状态的可能性。还提供了具有SiGe体或阱区的沟槽栅功率MOSFET器件。当体二极管导通时，SiGe体减小空穴电流，从而降低反向恢复功率损耗。其他装置特性也得到改善。例如，通过使用多晶SiGe栅极可以减小寄生栅极阻抗。此外，可以通过在器件栅极附近使用SiGe层来减小沟道电阻，并且可以在沟槽栅极下形成厚的氧化物区域以减小栅极 - 漏极电容。

5. 发明授权

US07544571B2 Trench gate FET with self-aligned features 有权
标题翻译：具有自对准特征的沟槽栅FET
公开(公告)号：US07544571B2
公开(公告)日：2009-06-09
申请号：US11536584
申请日：2006-09-28
申请人： Chanho Park
发明人： Chanho Park
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. A gate electrode recessed in each trench is formed. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.
摘要翻译：场效应晶体管如下形成。沟槽形成在第一导电类型的半导体区域中。形成凹陷在每个沟槽中的栅电极。使用第一掩模，通过注入掺杂剂在半导体区域中形成第二导电类型的体区。使用第一掩模，通过注入掺杂剂在体区中形成第一导电类型的源区。

6. 发明申请

US20120235230A1 MOSFET DEVICE WITH THICK TRENCH BOTTOM OXIDE 有权
标题翻译：具有厚度底部氧化物的MOSFET器件
公开(公告)号：US20120235230A1
公开(公告)日：2012-09-20
申请号：US13049629
申请日：2011-03-16
申请人： Chanho Park , Ashok Challa , Ritu Sodhi
发明人： Chanho Park , Ashok Challa , Ritu Sodhi
IPC分类号： H01L29/78 , H01L21/22
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66734
摘要： In one general aspect, an apparatus can include a first trench oxide disposed within a first trench of an epitaxial layer and having a trench bottom oxide disposed below a gate portion of the first trench oxide. The apparatus can include a second trench disposed lateral to the first trench. The trench bottom oxide portion of the first oxide can have a thickness greater than a distance within the epitaxial layer from the first trench to the second trench.
摘要翻译：在一个一般方面，装置可以包括设置在外延层的第一沟槽内并且具有设置在第一沟槽氧化物的栅极部分下方的沟槽底部氧化物的第一沟槽氧化物。该设备可以包括设置在第一沟槽侧面的第二沟槽。第一氧化物的沟槽底部氧化物部分可以具有大于外延层内的从第一沟槽到第二沟槽的距离的厚度。

7. 发明授权

US07935561B2 Method of forming shielded gate FET with self-aligned features 有权
标题翻译：形成具有自对准特征的屏蔽栅极FET的方法
公开(公告)号：US07935561B2
公开(公告)日：2011-05-03
申请号：US12480031
申请日：2009-06-08
申请人： Chanho Park
发明人： Chanho Park
IPC分类号： H01L23/60
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a shielded gate field effect transistor includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A shield electrode is formed in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric. A gate electrode recessed in each trench is formed over the shield electrode, the gate electrode being insulated from the shield electrode. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.
摘要翻译：一种用于形成屏蔽栅极场效应晶体管的方法包括以下步骤。沟槽形成在第一导电类型的半导体区域中。屏蔽电极形成在每个沟槽的底部，屏蔽电极通过屏蔽电介质与半导体区域绝缘。在屏蔽电极上方形成有凹陷在每个沟槽中的栅电极，栅电极与屏蔽电极绝缘。使用第一掩模，通过注入掺杂剂在半导体区域中形成第二导电类型的体区。使用第一掩模，通过注入掺杂剂在体区中形成第一导电类型的源区。

8. 发明申请

US20080124870A1 Trench Gate FET with Self-Aligned Features 审中-公开
标题翻译：具有自对准特征的沟槽栅FET
公开(公告)号：US20080124870A1
公开(公告)日：2008-05-29
申请号：US11533493
申请日：2006-09-20
申请人： Chanho Park
发明人： Chanho Park
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L21/266 , H01L29/1095 , H01L29/66348 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. A gate electrode recessed in each trench is formed. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.
摘要翻译：场效应晶体管如下形成。沟槽形成在第一导电类型的半导体区域中。形成凹陷在每个沟槽中的栅电极。使用第一掩模，通过注入掺杂剂在半导体区域中形成第二导电类型的体区。使用第一掩模，通过注入掺杂剂在体区中形成第一导电类型的源区。

9. 发明授权

US09425305B2 Structures of and methods of fabricating split gate MIS devices 有权
标题翻译：分离门MIS器件的结构和方法
公开(公告)号：US09425305B2
公开(公告)日：2016-08-23
申请号：US12869554
申请日：2010-08-26
申请人： Kyle Terrill , Yang Gao , Chanho Park
发明人： Kyle Terrill , Yang Gao , Chanho Park
IPC分类号： H01L29/78 , H01L29/40 , H01L29/66 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7811
摘要： A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly layer is disposed within the trench and is connected to the gate electrode. A second poly layer connected to the source electrode, wherein the first poly layer and the second poly layer are independent.
摘要翻译：分路栅场效应晶体管器件。该器件包括具有沟槽，栅电极和源电极的分离栅结构。第一多晶硅层设置在沟槽内并连接到栅电极。连接到源电极的第二多晶硅层，其中第一多晶硅层和第二多晶硅层是独立的。

10. 发明授权

US08598654B2 MOSFET device with thick trench bottom oxide 有权
标题翻译：具有厚沟槽底部氧化物的MOSFET器件
公开(公告)号：US08598654B2
公开(公告)日：2013-12-03
申请号：US13049629
申请日：2011-03-16
申请人： Chanho Park , Ashok Challa , Ritu Sodhi
发明人： Chanho Park , Ashok Challa , Ritu Sodhi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66734
摘要： In one general aspect, an apparatus can include a first trench oxide disposed within a first trench of an epitaxial layer and having a trench bottom oxide disposed below a gate portion of the first trench oxide. The apparatus can include a second trench disposed lateral to the first trench. The trench bottom oxide portion of the first oxide can have a thickness greater than a distance within the epitaxial layer from the first trench to the second trench.
摘要翻译：在一个一般方面，装置可以包括设置在外延层的第一沟槽内并且具有设置在第一沟槽氧化物的栅极部分下方的沟槽底部氧化物的第一沟槽氧化物。该设备可以包括设置在第一沟槽侧面的第二沟槽。第一氧化物的沟槽底部氧化物部分可以具有大于外延层内的从第一沟槽到第二沟槽的距离的厚度。

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