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1. 发明授权

US08680611B2 Field effect transistor and schottky diode structures 有权
标题翻译：场效应晶体管和肖特基二极管结构
公开(公告)号：US08680611B2
公开(公告)日：2014-03-25
申请号：US13600184
申请日：2012-08-30
申请人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
发明人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
IPC分类号： H01L29/76
CPC分类号： H01L29/7827 , H01L21/26586 , H01L27/0629 , H01L29/0619 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66666 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7828 , H01L29/872 , H01L2924/13091
摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.
摘要翻译：根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。导体层可与半导体区形成肖特基接触。

2. 发明申请

US20120319197A1 FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES 有权
标题翻译：场效应晶体管和肖特基二极管结构
公开(公告)号：US20120319197A1
公开(公告)日：2012-12-20
申请号：US13600184
申请日：2012-08-30
申请人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
发明人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L21/26586 , H01L27/0629 , H01L29/0619 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66666 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7828 , H01L29/872 , H01L2924/13091
摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.
摘要翻译：根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。导体层可与半导体区形成肖特基接触。

3. 发明申请

US20120274402A1 HIGH ELECTRON MOBILITY TRANSISTOR 审中-公开
标题翻译：高电子移动晶体管
公开(公告)号：US20120274402A1
公开(公告)日：2012-11-01
申请号：US13455626
申请日：2012-04-25
申请人： CHRISTOPHER BOGUSLAW KOCON
发明人： CHRISTOPHER BOGUSLAW KOCON
IPC分类号： H03F3/16 , H01L29/778
CPC分类号： H01L29/7787 , H01L29/402 , H01L29/404 , H01L29/41766
摘要： A high electron mobility transistor (HEMT) includes a substrate, a heterojunction on the substrate including a first layer having a Group III-nitride semiconductor material interfaced to a second layer having a doped Group III-nitride semiconductor material. A gate electrode is on a surface of the heterojunction, and a source and a drain are on opposite sides of said gate electrode. A patterned field shaping (FS) layer formed from a wide band-gap semiconductor material is over the heterojunction on at least a portion between the gate electrode and the drain.
摘要翻译：高电子迁移率晶体管（HEMT）包括衬底，衬底上的异质结，包括具有与具有掺杂的III族氮化物半导体材料的第二层相连的III族氮化物半导体材料的第一层。栅电极在异质结的表面上，源极和漏极位于所述栅电极的相对侧上。由宽带隙半导体材料形成的图案化场成形（FS）层在栅电极和漏极之间的至少一部分上超过异质结。

4. 发明申请

US20120133016A1 LATERAL POWER DIODE WITH SELF-BIASING ELECTRODE 有权
标题翻译：具有自偏电极的侧向功率二极管
公开(公告)号：US20120133016A1
公开(公告)日：2012-05-31
申请号：US13365983
申请日：2012-02-03
申请人： Christopher Boguslaw Kocon
发明人： Christopher Boguslaw Kocon
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/407 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/41766 , H01L29/7816 , H01L29/7824
摘要： A schottky diode includes a drift region of a first conductivity type and a lightly doped silicon region of the first conductivity type in the drift region. A conductor layer is over and in contact with the lightly doped silicon region to form a schottky contact with the lightly doped silicon region. A highly doped silicon region of the first conductivity type is in the drift region and is laterally spaced from the lightly doped silicon region such that upon biasing the schottky diode in a conducting state, a current flows laterally between the lightly doped silicon region and the highly doped silicon region through the drift region. A plurality of trenches extend into the drift region perpendicular to the current flow. Each trench has a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.
摘要翻译：肖特基二极管包括漂移区中第一导电类型的漂移区和第一导电类型的轻掺杂硅区。导体层与轻掺杂的硅区域结合并接触，以与轻掺杂的硅区域形成肖特基接触。第一导电类型的高掺杂硅区域在漂移区域中并且与轻掺杂硅区域横向间隔开，使得在将肖特基二极管偏置在导通状态中时，电流在轻掺杂硅区域和高度掺杂的硅区域之间横向流动掺杂硅区域通过漂移区域。多个沟槽延伸到垂直于电流的漂移区域中。每个沟槽具有内衬至少一部分沟槽侧壁和至少一个导电电极的电介质层。

5. 发明申请

US20110177662A1 Method of Forming Trench-Gate Field Effect Transistors 有权
标题翻译：形成沟槽栅场效应晶体管的方法
公开(公告)号：US20110177662A1
公开(公告)日：2011-07-21
申请号：US13075091
申请日：2011-03-29
申请人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
发明人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
摘要翻译：形成场效应晶体管的方法包括：在半导体区域中形成沟槽; 在沟槽中形成屏蔽电极; 执行第一导电类型的杂质的成角度的侧壁注入，以形成与沟槽相邻的沟道增强区域; 在半导体区域中形成第二导电类型的体区; 并且在所述体区域中形成所述第一导电类型的源极区域，所述源极区域和所述体区域与所述半导体区域之间的界面在所述体区域中形成沟道区域，所述沟道区域沿着所述沟槽侧壁延伸。沟道增强区域部分地延伸到沟道区的下部，从而减小沟道区的电阻。

6. 发明申请

US20100258862A1 TRENCH-GATE FIELD EFFECT TRANSISTOR WITH CHANNEL ENHANCEMENT REGION AND METHODS OF FORMING THE SAME 有权
标题翻译：具有通道增强区域的TRENCH-GATE场效应晶体管及其形成方法
公开(公告)号：US20100258862A1
公开(公告)日：2010-10-14
申请号：US12698746
申请日：2010-02-02
申请人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
发明人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
摘要翻译：场效应晶体管包括在第二导电类型的半导体区域中的第一导电类型的体区。栅极沟槽延伸穿过身体区域并终止在半导体区域内。第二导电类型的源极区域在与栅极沟槽相邻的体区中延伸。源极区域和主体区域和半导体区域之间的界面限定其间沿着栅极沟槽侧壁延伸的沟道区域。第二导电类型的沟道增强区域形成在栅极沟槽附近。沟道增强区域部分地延伸到沟道区的下部，从而减小沟道区的电阻。

7. 发明授权

US07595542B2 Periphery design for charge balance power devices 有权
标题翻译：电荷平衡功率器件的周边设计
公开(公告)号：US07595542B2
公开(公告)日：2009-09-29
申请号：US11375683
申请日：2006-03-13
申请人： Chanho Park , Joseph A. Yedinak , Christopher Boguslaw Kocon , Jason Higgs , Jaegil Lee
发明人： Chanho Park , Joseph A. Yedinak , Christopher Boguslaw Kocon , Jason Higgs , Jaegil Lee
IPC分类号： H01L29/93
CPC分类号： H01L29/0634 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.
摘要翻译：电荷平衡半导体功率器件包括有源区，其具有p柱的条带和以交替方式布置的n个柱的条带，沿着有源区的长度延伸的p和n柱的条带。非活动周边区域包围有源区域，并且包括围绕有源区域的至少一个p环。最后一根直立在有源区域边缘上的p柱条的一端终止于大致直线，其中p柱的每条剩余的条的一端也结束。直线垂直于有源区域的长度延伸，n和p柱的条带沿着该区域的长度延伸。

8. 发明授权

US07132712B2 Trench structure having one or more diodes embedded therein adjacent a PN junction 有权
标题翻译：沟槽结构，其中一个或多个二极管嵌入其中，邻近PN结
公开(公告)号：US07132712B2
公开(公告)日：2006-11-07
申请号：US10288982
申请日：2002-11-05
申请人： Christopher Boguslaw Kocon , Joseph Andrew Yedinak
发明人： Christopher Boguslaw Kocon , Joseph Andrew Yedinak
IPC分类号： H01L29/72
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/404 , H01L29/407 , H01L29/7802 , H01L29/7813 , H01L29/7818 , H01L29/861
摘要： In accordance with an embodiment of the invention, a semiconductor structure includes a semiconductor region having a P-type region and a N-type region forming a PN junction therebetween. A first trench extends in the semiconductor region adjacent at least one of the P-type and N-type regions. The first trench includes at least one diode therein.
摘要翻译：根据本发明的实施例，半导体结构包括具有P型区域和在其间形成PN结的N型区域的半导体区域。第一沟槽在邻近P型和N型区域中的至少一个的半导体区域中延伸。第一沟槽在其中包括至少一个二极管。

9. 发明授权

US07061066B2 Schottky diode using charge balance structure 有权
标题翻译：肖特基二极管采用电荷平衡结构
公开(公告)号：US07061066B2
公开(公告)日：2006-06-13
申请号：US10821796
申请日：2004-04-09
申请人： Christopher Boguslaw Kocon
发明人： Christopher Boguslaw Kocon
IPC分类号： H01L29/72
CPC分类号： H01L29/407 , H01L29/0653 , H01L29/0692 , H01L29/404 , H01L29/66143 , H01L29/861 , H01L29/872
摘要： In accordance with an embodiment of the invention, a Schottky diode includes a metal layer in contact with a semiconductor region to form a Schottky barrier therebetween. A first trench extends in the semiconductor region. The first trench includes at least one electrode or diode therein.
摘要翻译：根据本发明的实施例，肖特基二极管包括与半导体区域接触以在其间形成肖特基势垒的金属层。第一沟槽在半导体区域中延伸。第一沟槽在其中包括至少一个电极或二极管。

10. 发明授权

US5877044A Method of making MOS-gated semiconductor devices 失效
标题翻译：制造MOS门控半导体器件的方法
公开(公告)号：US5877044A
公开(公告)日：1999-03-02
申请号：US814842
申请日：1997-03-11
申请人： John Manning Savidge Neilson , Christopher Boguslaw Kocon , Richard Douglas Stokes , Linda Susan Brush , John Lawrence Benjamin , Louise Ellen Skurkey , Christopher Lawrence Rexer
发明人： John Manning Savidge Neilson , Christopher Boguslaw Kocon , Richard Douglas Stokes , Linda Susan Brush , John Lawrence Benjamin , Louise Ellen Skurkey , Christopher Lawrence Rexer
IPC分类号： H01L29/78 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L21/332
CPC分类号： H01L29/66333 , H01L29/0696 , H01L29/1095 , H01L29/7802
摘要： A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholly enclosing a third heavily doped (body) region partly enclosing the first region, and a fourth (drain) region forming a P-N junction with the third region. The gate electrode control structure is fabricated using known gate electrode self-alignment doping processes but wherein, in the process for forming the third heavily doped region, a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision.
摘要翻译： MOS门控半导体器件的栅极电极控制结构包括四个掺杂区域，其包括形成第一PN结的第一（源极）区域，该第一PN结区域与封闭的复合区域包括完全包围第三重掺杂（沟道）区域的第二轻掺杂部分地包围第一区域的第一（主体）区域和与第三区域形成PN结的第四（漏极）区域。使用已知的栅电极自对准掺杂工艺制造栅电极控制结构，但是在用于形成第三重掺杂区的工艺中，在栅电极上设置间隔层，用于限定第三区与沟道之间的间隔区域精度提高。

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