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1. 发明授权

US07334137B2 Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller 有权
标题翻译：将存储器耦合到存储器控制器并且响应于与存储器和存储器控制器的电源电压无关的端子电压的存储器接口系统
公开(公告)号：US07334137B2
公开(公告)日：2008-02-19
申请号：US09851277
申请日：2001-05-08
申请人： Tae-sung Jung , Byung-se So , Myun-joo Park
发明人： Tae-sung Jung , Byung-se So , Myun-joo Park
IPC分类号： G06F1/00 , G11C7/00 , G11C7/02 , H02J1/10 , H02J1/00
CPC分类号： G11C7/1084 , G06F13/1668 , G06F13/4086 , G11C7/1078 , Y10T307/383 , Y10T307/658 , Y10T307/669 , Y10T307/675
摘要： Memory interface systems include one or more channel lines that couple a memory to a memory controller such that the channel line(s) are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller. Because the memory interface system uses a terminal voltage that is independent of the supply voltages of the memory and the memory controller, the interface system may be unaffected by voltage differences between the memory supply voltage and the memory controller supply voltage.
摘要翻译：存储器接口系统包括将存储器耦合到存储器控制器的一个或多个通道线，使得通道线响应于独立于存储器和存储器控制器的电源电压的端子电压。因为存储器接口系统使用独立于存储器和存储器控制器的电源电压的端子电压，所以接口系统可以不受存储器电源电压和存储器控制器电源电压之间的电压差的影响。

2. 发明授权

US06480409B2 Memory modules having integral terminating resistors and computer system boards for use with same 有权
标题翻译：具有集成终端电阻和与其一起使用的计算机系统板的存储器模块
公开(公告)号：US06480409B2
公开(公告)日：2002-11-12
申请号：US09858401
申请日：2001-05-16
申请人： Myun-joo Park , Byung-se So
发明人： Myun-joo Park , Byung-se So
IPC分类号： G11C506
CPC分类号： G11C5/063 , G06F13/4086
摘要： A memory module for use with a computer system board includes at least one memory chip connected to a bus line conductor and a terminating resistor connected to the bus line conductor. The memory module further includes a connector configured to connect the bus line conductor to bus line of the computer system board. A computer system board includes a bus line including first branch configured to connect to a first memory module and a second branch configured to connect to a second memory module. The computer system board further includes a memory controller coupled to the first and second branches of the bus line at a single pin thereof. In other embodiments, a computer system board includes a bus line having first and second branches. A first switch is operative to selectively couple a first plurality of memory modules to a first branch of a bus line of the system board. A second switch is operative to selectively couple a second plurality of memory modules to the second branch of the bus line. The system board further includes a memory controller connected to the first and second branches of the bus line at a single pin thereof.
摘要翻译：与计算机系统板一起使用的存储器模块包括连接到总线导体的至少一个存储器芯片和连接到总线导线的终端电阻器。存储器模块还包括被配置为将总线导线连接到计算机系统板的总线的连接器。计算机系统板包括总线，其包括被配置为连接到第一存储器模块的第一分支和被配置为连接到第二存储器模块的第二分支。计算机系统板还包括存储器控制器，其在其一个引脚处耦合到总线线路的第一和第二分支。在其他实施例中，计算机系统板包括具有第一和第二分支的总线。第一开关用于选择性地将第一多个存储器模块耦合到系统板的总线的第一分支。第二开关用于选择性地将第二多个存储器模块耦合到总线线路的第二分支。系统板还包括一个存储器控制器，该存储器控制器在其一个引脚处连接到总线的第一和第二分支。

3. 发明授权

US06772262B1 Memory module with improved data bus performance 有权
公开(公告)号：US06772262B1
公开(公告)日：2004-08-03
申请号：US09777446
申请日：2001-02-06
申请人： Myun-joo Park , Byung-se So
发明人： Myun-joo Park , Byung-se So
IPC分类号： G11C800
CPC分类号： H05K1/0216 , G06F13/1684 , G11C5/04 , G11C5/06 , H05K1/117 , H05K1/141 , H05K2201/09254 , H05K2201/10159 , H05K2203/1572
摘要： A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

4. 发明授权

US06990543B2 Memory module with improved data bus performance 有权
标题翻译：内存模块具有改进的数据总线性能
公开(公告)号：US06990543B2
公开(公告)日：2006-01-24
申请号：US10883488
申请日：2004-07-01
申请人： Myun-joo Park , Byung-se So
发明人： Myun-joo Park , Byung-se So
IPC分类号： G11C8/00
CPC分类号： H05K1/0216 , G06F13/1684 , G11C5/04 , G11C5/06 , H05K1/117 , H05K1/141 , H05K2201/09254 , H05K2201/10159 , H05K2203/1572
摘要： A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.
摘要翻译：存储器模块能够构成可以减少整个通道的长度的短循环形式的存储器总线系统。结果，该系统适用于高速操作，并且可以减少制造诸如板和模块连接器的系统的成本。存储器模块包括位于存储器模块的前部和后侧的一侧中的多个突片，用于通过系统板上的连接器互连，用于连接两个不同信号层的多个通孔存储器模块和多个数据总线通过每个通孔从存储器模块的前面的突出部延伸到存储器模块的后部上的突出部。至少一个存储器件连接到每个数据总线。优选地，每个数据总线形成为垂直于其上形成有突片的存储器模块的一侧。

5. 发明授权

US06414904B2 Two channel memory system having shared control and address bus and memory modules used therefor 失效
标题翻译：具有共享控制和地址总线的双通道存储器系统和用于其的存储器模块
公开(公告)号：US06414904B2
公开(公告)日：2002-07-02
申请号：US09777547
申请日：2001-02-06
申请人： Byung-se So , Myun-joo Park , Sang-won Lee
发明人： Byung-se So , Myun-joo Park , Sang-won Lee
IPC分类号： G11C800
CPC分类号： G11C5/025 , H01L2224/16225
摘要： A memory system, which can improve the operation speed of a data bus and is suitable for widening bandwidth by extending the width of the data bus, and memory modules used for the memory system are provided. In the memory system, data buses of a first channel and data buses of a second channel are extended from a memory controller and are arranged on the left and right of a common control and address bus, respectively. Memory modules of a first group are loaded in the data buses of the first channel and memory modules of a second group are loaded in the data buses of the second channel. Also, in the memory system, the memory modules share the common control and address bus positioned in the center. Also, the memory modules are arranged so that some parts of the memory modules overlap each other and that the memory modules of the first group and the memory modules of the second group cross each other. Each of the memory modules includes a plurality of memory devices mounted on the memory module, a signal input and output portion positioned on a side of the memory module, the signal input and output portion for connecting the memory module to a connector on a system board, a buffer mounted on the memory module, and a control and address bus connected between the signal input and output portion and the buffer. The memory devices are sequentially connected to the output line of the buffer so that a signal that passed through the control and address bus is input to the respective memory devices at time intervals through the buffer.
摘要翻译：一种存储器系统，其可以提高数据总线的操作速度，并且适用于通过扩展数据总线的宽度来扩大带宽，并且提供用于存储器系统的存储器模块。在存储器系统中，第一通道的数据总线和第二通道的数据总线从存储器控制器扩展并分别布置在公共控制和地址总线的左侧和右侧。第一组的存储器模块被加载到第一通道的数据总线中，第二组的存储器模块被加载到第二通道的数据总线中。此外，在存储器系统中，存储器模块共享位于中心的公共控制和地址总线。此外，存储器模块被布置成使得存储器模块的一些部分彼此重叠，并且第一组的存储器模块和第二组的存储器模块彼此交叉。每个存储器模块包括安装在存储器模块上的多个存储器件，位于存储器模块一侧的信号输入和输出部分，用于将存储器模块连接到系统板上的连接器的信号输入和输出部分，安装在存储器模块上的缓冲器，以及连接在信号输入和输出部分与缓冲器之间的控制和地址总线。存储器件顺序地连接到缓冲器的输出线，使得通过控制和地址总线的信号通过缓冲器以时间间隔输入到各个存储器件。

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