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1. 外观设计

USD654478S1 Remote controller for TV receiver 有权
标题翻译：电视接收机遥控器
公开(公告)号：USD654478S1
公开(公告)日：2012-02-21
申请号：US29405087
申请日：2011-10-28
申请人： Chang-Soo Noh , You-Sun Ji , Se-Ra Park , Sang-On Choi , Eun-Seok Choi
设计人： Chang-Soo Noh , You-Sun Ji , Se-Ra Park , Sang-On Choi , Eun-Seok Choi

2. 发明授权

US06913967B2 Ferroelectric memory device with merged-top plate structure and method for fabricating the same 有权
标题翻译：具有合并顶板结构的铁电存储器件及其制造方法
公开(公告)号：US06913967B2
公开(公告)日：2005-07-05
申请号：US10623098
申请日：2003-07-18
申请人： Eun-Seok Choi , Seung-Jin Yeom
发明人： Eun-Seok Choi , Seung-Jin Yeom
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/60 , H01L28/65 , H01L28/75
摘要： The inventive ferroelectric memory device includes: a semiconductor substrate providing elements of a transistor; a first inter-layer insulating layer formed on the semiconductor substrate; a storage node contact connected to elements of the transistor by passing through the first inter-layer insulating layer; a barrier layer contacting simultaneously to the storage node contact and the first inter-layer insulating layer; a lower electrode having a space for isolating the first inter-layer insulating layer and being formed on the barrier layer; a glue layer being formed on the first inter-layer insulating layer and encompassing lateral sides of the lower electrode as filling the space; a second inter-layer insulating layer exposing a surface of the lower electrode and encompassing the glue layer; a ferroelectric layer formed on the glue layer including the second inter-layer insulating layer; and an upper electrode formed on the ferroelectric layer.
摘要翻译：本发明的铁电存储器件包括：提供晶体管元件的半导体衬底; 形成在所述半导体基板上的第一层间绝缘层; 通过穿过所述第一层间绝缘层而连接到所述晶体管的元件的存储节点接触; 与所述存储节点接触部和所述第一层间绝缘层同时接触的阻挡层; 具有用于隔离所述第一层间绝缘层并形成在所述阻挡层上的空间的下电极; 胶层在第一层间绝缘层上形成，并且在下部电极的横向侧面填充空间; 第二层间绝缘层，暴露下电极的表面并包围胶层; 形成在包括第二层间绝缘层的胶层上的铁电层; 以及形成在强电介质层上的上电极。

3. 发明授权

US06891211B2 Ferroelectric random access memory device and method for fabricating the same 有权
标题翻译：铁电随机存取存储器件及其制造方法
公开(公告)号：US06891211B2
公开(公告)日：2005-05-10
申请号：US10612914
申请日：2003-07-07
申请人： Seung-Jin Yeom , Eun-Seok Choi
发明人： Seung-Jin Yeom , Eun-Seok Choi
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/115 , H01L31/062
CPC分类号： H01L27/11502 , H01L27/11507
摘要： The present invention is related to a ferroelectric memory device and a method for fabricating the same. The ferroelectric memory device includes: a substrate providing a transistor; a first insulation material with a plane surface formed on the substrate; a storage node contact passing through the first insulation material to contact to an active region of the substrate; a lower electrode being connected to the storage node contact and including a solid solution layer disposed at least as an upper most layer, the solid solution layer being doped with a metal element, which is induced to be in a solid solution state; a second insulation material having a plane surface that exposes a surface of the lower electrode, encompassing the lower electrode and being formed on the first insulation material; a ferroelectric layer covering the second insulation material including the lower electrode; an upper electrode formed on the ferroelectric layer.
摘要翻译：本发明涉及铁电存储器件及其制造方法。铁电存储器件包括：提供晶体管的衬底; 在所述基板上形成有平面的第一绝缘材料; 存储节点接触件穿过所述第一绝缘材料以接触所述衬底的有源区; 下部电极连接到存储节点接触并且包括至少设置为最上层的固溶体层，所述固溶体层掺杂有被诱导为固溶状态的金属元素; 第二绝缘材料，其具有暴露下部电极的表面的平面，包围下部电极并形成在第一绝缘材料上; 覆盖包括下电极的第二绝缘材料的铁电层; 形成在强电介质层上的上电极。

4. 发明授权

US09287283B2 Non-volatile memory device and method for fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US09287283B2
公开(公告)日：2016-03-15
申请号：US13462082
申请日：2012-05-02
申请人： Se-Yun Lim , Eun-Seok Choi , Young-Wook Lee , Won-Joon Choi , Ki-Hong Lee , Sang-Bum Lee
发明人： Se-Yun Lim , Eun-Seok Choi , Young-Wook Lee , Won-Joon Choi , Ki-Hong Lee , Sang-Bum Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582
摘要： A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.
摘要翻译：一种用于制造非易失性存储器件的方法包括在衬底上交替堆叠多个层间电介质层和多个导电层，蚀刻层间电介质层和导电层以形成暴露衬底形成表面的沟槽在其中形成沟槽的结果结构上的第一材料层，在第一材料层上形成第二材料层，去除第二材料层的部分和形成在沟槽的底部上的第一材料层，以暴露出衬底，去除第二材料层，以及在去除第二材料层的沟槽内掩埋沟道层。

5. 发明授权

US08675404B2 Reading method of non-volatile memory device 有权
标题翻译：非易失性存储器件的读取方法
公开(公告)号：US08675404B2
公开(公告)日：2014-03-18
申请号：US13475204
申请日：2012-05-18
申请人： Hyun-Seung Yoo , Sung-Joo Hong , Seiichi Aritome , Seok-Kiu Lee , Sung-Kye Park , Gyu-Seog Cho , Eun-Seok Choi , Han-Soo Joo
发明人： Hyun-Seung Yoo , Sung-Joo Hong , Seiichi Aritome , Seok-Kiu Lee , Sung-Kye Park , Gyu-Seog Cho , Eun-Seok Choi , Han-Soo Joo
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3418
摘要： A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.
摘要翻译：一种非易失性存储器件的读取方法，包括分别包括一个浮动栅极和两个控制栅极的多个存储器单元，两个控制栅极分别与浮置栅极的两个交替侧相邻设置，并且两个相邻的存储单元共享一个所述读取方法包括将读取电压施加到所选择的存储器单元的控制栅极，将第二通过电压施加到与所选择的存储器单元的控制栅极不同的存储单元的控制栅极的替代控制栅极，所述存储器单元从控制栅极开始，所选择的存储单元，以及施加低于第二通过电压的第一通过电压，以从控制栅极开始的第二选择的存储单元开始，将不同于所选存储单元的控制栅极的存储单元的控制栅极交替。

6. 发明授权

US08482055B2 Non-volatile memory device and method for fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08482055B2
公开(公告)日：2013-07-09
申请号：US13304901
申请日：2011-11-28
申请人： Eun-Seok Choi , Hyun-Seung Yoo
发明人： Eun-Seok Choi , Hyun-Seung Yoo
IPC分类号： H01L29/792 , H01L21/336 , H01L29/78
CPC分类号： H01L27/11582 , H01L27/11575 , H01L28/20
摘要： A non-volatile memory device includes a substrate including a resistor layer having a resistance lower than that of a source line, channel structures including a plurality of inter-layer dielectric layers that are alternately staked with a plurality of channel layers over the substrate, and the source line configured to contact sidewalls of the channel layers, where a lower end of the source line contacts the resistor layer.
摘要翻译：非易失性存储器件包括：衬底，其具有电阻低于源极线的电阻层，沟道结构包括多个层间电介质层，所述多个层间电介质层与衬底上的多个沟道层交替地淀积;以及源极线被配置为接触沟道层的侧壁，其中源极线的下端接触电阻层。

7. 发明授权

US08482051B2 3D nonvolatile memory device including a plurality of channel contacts coupled to a plurality of channel layers and a plurality of section lines coupled to the plurality of channel contacts and method for fabricating the same 有权
标题翻译： 3D非易失性存储器件包括耦合到多个沟道层的多个沟道触点和耦合到多个沟道触点的多个选择线及其制造方法
公开(公告)号：US08482051B2
公开(公告)日：2013-07-09
申请号：US12974397
申请日：2010-12-21
申请人： Se-Yun Lim , Eun-Seok Choi
发明人： Se-Yun Lim , Eun-Seok Choi
IPC分类号： H01L29/78
CPC分类号： H01L27/11573 , H01L27/105 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： A 3D nonvolatile memory device includes a plurality of channel structures each comprising a plurality of channel layers and interlayer dielectric layers which are alternately stacked, a plurality of channel contacts coupled to the plurality of channel layers, respectively, and a plurality of selection lines vertically-coupled to the plurality of channel contacts and crossing over the plurality of channel structures.
摘要翻译： 3D非易失性存储器件包括多个沟道结构，每个沟道结构包括交替层叠的多个沟道层和层间电介质层，分别耦合到多个沟道层的多个沟道触点，以及多个选择线，耦合到所述多个通道触点并跨过所述多个通道结构。

8. 发明申请

US20110199813A1 NON-VOLATILE MEMORY DEVICE HAVING 3D STRUCTURE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：具有3D结构的非易失性存储器件及其制造方法
公开(公告)号：US20110199813A1
公开(公告)日：2011-08-18
申请号：US12980983
申请日：2010-12-29
申请人： Hyun-Seung Yoo , Eun-Seok Choi
发明人： Hyun-Seung Yoo , Eun-Seok Choi
IPC分类号： G11C11/00 , H01L21/8242
CPC分类号： H01L27/249 , G11C5/02 , G11C13/0004 , G11C13/0007 , G11C14/00 , G11C2213/71 , H01L27/2409 , H01L27/2454
摘要： A non-volatile memory device having a three-dimensional (3D) structure includes a plurality of line-type horizontal electrode structures configured to include a plurality of interlayer dielectric layers and a plurality of horizontal electrodes that are alternately stacked over a substrate, a plurality of pillar-type vertical electrodes configured to protrude from the substrate while contacting sidewalls of the plurality of the horizontal electrode structures, and a memory layer interposed between the plurality of the horizontal electrode structures and the plurality of the vertical electrodes, and configured to have a resistance value that varies based on a bias applied to the plurality of the horizontal electrodes and the plurality of the vertical electrodes.
摘要翻译：具有三维（3D）结构的非易失性存储器件包括多个线型水平电极结构，其被配置为包括交替层叠在衬底上的多个层间电介质层和多个水平电极，多个构成为从所述基板突出而同时接触所述多个所述水平电极结构的侧壁的柱状垂直电极;以及插入在所述多个所述水平电极结构体与所述多个所述垂直电极之间的存储层，电阻值基于施加到多个水平电极和多个垂直电极的偏压而变化。

9. 发明申请

US20080136344A1 LAMP DRIVING DEVICE AND DISPLAY APPARATUS HAVING THE SAME 失效
标题翻译：灯具驱动装置和具有该装置的显示装置
公开(公告)号：US20080136344A1
公开(公告)日：2008-06-12
申请号：US11929223
申请日：2007-10-30
申请人： Moon-Shik Kang , Myung-Joong Youn , Jheen-Hyeok Park , Gun-Woo Moon , Hyun-Ki Yoon , Eun-Seok Choi
发明人： Moon-Shik Kang , Myung-Joong Youn , Jheen-Hyeok Park , Gun-Woo Moon , Hyun-Ki Yoon , Eun-Seok Choi
IPC分类号： H05B41/26
CPC分类号： H05B41/2881
摘要： A lamp driving device includes first, second, and third voltage converters. The first voltage converter converts a direct current (DC) power voltage to a first pulse voltage. The second voltage converter converts the DC power voltage to a second pulse voltage. The third voltage converter generates a high alternating current (AC) voltage based on the first and second pulse voltages. The lamp driving device generates the high AC voltage without a transformer, so that a manufacturing cost of a display apparatus adopting the lamp driving device may be reduced.
摘要翻译：灯驱动装置包括第一，第二和第三电压转换器。第一电压转换器将直流（DC）电源电压转换为第一脉冲电压。第二电压转换器将DC电源电压转换成第二脉冲电压。第三电压转换器基于第一和第二脉冲电压产生高交流（AC）电压。灯驱动装置在没有变压器的情况下产生高交流电压，从而可以减少采用灯驱动装置的显示装置的制造成本。

10. 发明授权

US06524868B2 Method for fabricating semiconductor memory device 有权
标题翻译：半导体存储器件的制造方法
公开(公告)号：US06524868B2
公开(公告)日：2003-02-25
申请号：US09892537
申请日：2001-06-28
申请人： Eun-Seok Choi , Seung-Jin Yeom
发明人： Eun-Seok Choi , Seung-Jin Yeom
IPC分类号： H01L2100
CPC分类号： H01L28/75 , H01L28/55 , H01L28/60
摘要： A semiconductor memory device is provided which prevents a lifting phenomenon by improving an adhesive strength between an upper electrode and an interlayer insulating layer. The semiconductor memory device includes a capacitor formed on a semiconductor substrate, wherein the capacitor includes a lower electrode, a dielectric layer and an upper electrode; an adhesion layer formed on the upper electrode; an interlayer insulating layer covering the capacitor, wherein a portion of the interlayer insulating layer is in contact with the adhesion layer; and a contact hole, formed within the interlayer insulating layer, whose bottom exposes the upper electrode and whose sidewalls expose the interlayer insulating layer and the adhesion layer.
摘要翻译：提供一种半导体存储器件，其通过提高上部电极和层间绝缘层之间的粘合强度来防止提升现象。半导体存储器件包括形成在半导体衬底上的电容器，其中电容器包括下电极，电介质层和上电极; 形成在上电极上的粘附层; 覆盖电容器的层间绝缘层，其中层间绝缘层的一部分与粘合层接触; 以及形成在所述层间绝缘层内的接触孔，所述接触孔的底部暴露所述上部电极，并且其侧壁暴露所述层间绝缘层和所述粘合层。

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