专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06400932B1 Low offset automatic frequency tuning circuits for continuous-time filter 有权
标题翻译：低偏移自动频率调谐电路，用于连续时间滤波
公开(公告)号：US06400932B1
公开(公告)日：2002-06-04
申请号：US09454389
申请日：1999-12-03
申请人： Chang Jun Oh , Jong Kee Kwon , Jong Ryul Lee , Won Chul Song , Hee Bum Jung , Kyung Soo Kim , Han Jin Cho , Ook Kim
发明人： Chang Jun Oh , Jong Kee Kwon , Jong Ryul Lee , Won Chul Song , Hee Bum Jung , Kyung Soo Kim , Han Jin Cho , Ook Kim
IPC分类号： H04B118
CPC分类号： H03H11/0422 , H03L7/06
摘要： The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter. According to the invention, a frequency tuning circuit is provided which comprises integrating means for generating a signal discharging from a first reference voltage to a first predetermined value and a signal charging from a second reference voltage to a second predetermined value; offset sampling means for sampling the offset voltages of the Gm cells by receiving a current multiplied by the offset voltages from the Gm cells included in the integrating means and providing a feedback path between the output nodes and the input nodes of the included Gm cells; comparative signal generating means for generating a comparative signal by generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and comparing the actual intersection and the target intersection of these signals; and control means for generating a control signal to regulate the Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting the phase differences therebetween.
摘要翻译：调谐电路技术领域本发明涉及一种调谐电路，更具体地说涉及一种用于连续时间滤波器的调谐电路，其能够精确地确定Gm值，以使由于Gm-C型连续时间滤波器中的工艺变化引起的截止频率的变化最小化，时间过滤器。根据本发明，提供了一种频率调谐电路，其包括用于产生从第一参考电压放电到第一预定值的信号的积分装置和从第二参考电压到第二预定值的信号充电; 偏移采样装置，用于通过接收与积分装置中包括的Gm单元的偏移电压相乘的电流来对Gm单元的偏移电压进行采样，并在输出节点和所包括的Gm单元的输入节点之间提供反馈路径; 比较信号发生装置，用于通过将从外部输入的时钟分频，将从第一参考电压放电的信号接收到第一预定值和从第二参考电压到第二预定值的信号充电来产生参考信号，从积分装置获取值，并比较这些信号的实际交点和目标交点; 以及控制装置，用于通过从比较信号发生装置接收参考信号和比较信号并检测它们之间的相位差，产生控制信号以调节积分装置和偏移采样装置的Gm值。

2. 发明授权

US6069537A Double mode modulator 失效
标题翻译：双模式调制器
公开(公告)号：US6069537A
公开(公告)日：2000-05-30
申请号：US124142
申请日：1998-07-29
申请人： Ook Kim , Jong Kee Kwon , Jong Ryul Lee , Chang Jun Oh , Won Chul Song , Kyung Soo Kim
发明人： Ook Kim , Jong Kee Kwon , Jong Ryul Lee , Chang Jun Oh , Won Chul Song , Kyung Soo Kim
IPC分类号： H04B1/00 , H04B1/40 , H04L27/00 , H04L27/20 , H04L27/32
CPC分类号： H04L27/0008 , H04B1/406 , H04L27/2071 , H04B1/00
摘要： A double mode modulator, particularly, for a portable telephone, which is adapted to realize both digital and analog modulations and have a low phase noise and a reduced locking time with a device readily integrated in an integrated circuit, including: a frequency synthesizer for synthesizing a particular frequency from an external reference clock signal; a digital modulator for performing a quadrature modulation for an output signal of the frequency synthesizer; and an analog modulator for performing a frequency modulation for the output signal of the frequency synthesizer.
摘要翻译：一种双模式调制器，特别是用于便携式电话，其适于实现数字和模拟调制，并且具有低相位噪声和减少的锁定时间，其中易于集成在集成电路中的器件包括：用于合成的频率合成器来自外部参考时钟信号的特定频率; 用于对频率合成器的输出信号执行正交调制的数字调制器; 以及用于对频率合成器的输出信号执行频率调制的模拟调制器。

3. 发明授权

US6091289A Low pass filter 失效
标题翻译：低通滤波器
公开(公告)号：US6091289A
公开(公告)日：2000-07-18
申请号：US99388
申请日：1998-06-18
申请人： Won Chul Song , Jong Ryul Lee , Chang Jun Oh , Jong Kee Kwon , Ook Kim , Kyung Soo Kim
发明人： Won Chul Song , Jong Ryul Lee , Chang Jun Oh , Jong Kee Kwon , Ook Kim , Kyung Soo Kim
IPC分类号： H03H9/46 , H03H11/04 , H03K5/00
CPC分类号： H03H11/04
摘要： There is disclosed a low frequency filter. A low frequency cutoff filter includes a filter circuit having a capacitor connected between an input terminal and an output terminal and an active resistor connected to the output terminal, having a very large resistance, and a bias circuit having a negative feedback to set a biasing voltage of the active resistor to a desired value, thereby implementing the cutoff filter within a semiconductor chip as one set with the capacitor having a small capacitance. A low frequency pass filter includes an active resistor having a very large resistance, means for setting a biasing voltage of the active resistor to a desired value, and a capacitor connected between the output terminal and the ground. Therefore, the low pass filter can be integrated-circuited using even small capacitor.
摘要翻译：公开了一种低频滤波器。低频截止滤波器包括滤波器电路，其具有连接在输入端子和输出端子之间的电容器和连接到具有非常大电阻的输出端子的有源电阻器，以及具有负反馈以设置偏置电压的偏置电路将所述有源电阻器设置为期望值，从而在半导体芯片内实现截止滤波器作为一组，其中电容器具有小电容。低通滤波器包括具有非常大电阻的有源电阻器，用于将有源电阻器的偏置电压设置为期望值的装置，以及连接在输出端子和地之间的电容器。因此，低通滤波器可以使用甚至小的电容器集成。

4. 发明授权

US6011425A CMOS offset trimming circuit and offset generation circuit 失效
标题翻译： CMOS偏移调整电路和偏移生成电路
公开(公告)号：US6011425A
公开(公告)日：2000-01-04
申请号：US893459
申请日：1997-07-11
申请人： Chang-Jun Oh , Ook Kim , Jong-Kee Kwon , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
发明人： Chang-Jun Oh , Ook Kim , Jong-Kee Kwon , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
IPC分类号： H03K19/00 , G11C17/18 , H01H37/76
CPC分类号： G11C17/18
摘要： A CMOS offset trimming circuit and offset generation circuit for obtaining the corrected optimum offset value for correcting the offset generated in the CMOS analog circuit. An offset trimming circuit comprises a flip-flop for loading a data to be used for obtaining an optimum offset value or a data to be trimmed according to an input clock, a fuse circuit for setting the circuit with a corrected optimum offset value obtained in a corresponding mode by receiving the data loaded on the flip-flop and the mode selection signal as an input signal, and a selection logic circuit for outputting a selected signal as a trimming output signal by selecting one from the group consisting of the data loaded on the flip-flop and the data output from the fuse circuit according to the operation mode.
摘要翻译： CMOS偏移调整电路和偏移生成电路，用于获得用于校正在CMOS模拟电路中产生的偏移的校正的最佳偏移值。偏移修整电路包括用于根据输入时钟加载要用于获得最佳偏移值的数据或要修整的数据的触发器，用于设置具有校正的最佳偏移值的电路的熔丝电路，通过接收加载在触发器上的数据和模式选择信号作为输入信号的相应模式，以及选择逻辑电路，用于通过从由加载在所述触发器上的数据组合的组中选择一个来选择所选择的信号作为微调输出信号触发器和根据操作模式从熔丝电路输出的数据。

5. 发明授权

US5886550A Integrated circuit built-in type supply power delay circuit 失效
标题翻译：集成电路内置式电源延时电路
公开(公告)号：US5886550A
公开(公告)日：1999-03-23
申请号：US877408
申请日：1997-06-16
申请人： Jong-Kee Kwon , Gyu-Dong Kim , Ook Kim , Chang-Jun Oh , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
发明人： Jong-Kee Kwon , Gyu-Dong Kim , Ook Kim , Chang-Jun Oh , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
IPC分类号： G11C5/14 , H03K17/22
CPC分类号： H03K17/223
摘要： An integrated circuit built-in type power delay circuit which is capable of supplying a stable supply power to each circuit of the integrated circuit by generating a supply power control signal voltage after a predetermined time. The circuit includes a receiving unit for receiving a supply voltage VDD and charging the same, a supplying unit for supplying a current, an inverting unit for inverting an output value from the charging unit, a switching unit controlled in accordance with an output value from the inverting unit for switching an output from the current supply unit, a current regenerating unit for receiving a control of the switching unit and discharging an output value from the charging unit, an electric potential value conversion unit controlled by an output value from the inverting unit for converting an output value from the charging unit into a low level, and a buffering unit for receiving an output value from the inverting unit for buffering the output value and outputting a non-inverted signal.
摘要翻译：一种集成电路内置型功率延迟电路，其能够通过在预定时间之后产生电源功率控制信号电压来向集成电路的每个电路提供稳定的供电。该电路包括：接收单元，用于接收电源电压VDD并对其进行充电;提供单元，用于提供电流;反相单元，用于反转来自充电单元的输出值;开关单元，根据来自用于切换来自电流供应单元的输出的反相单元，用于接收开关单元的控制并从充电单元放电输出值的电流再生单元，由来自反相单元的输出值控制的电位值转换单元，将来自充电单元的输出值转换为低电平;以及缓冲单元，用于从反相单元接收输出值，用于缓冲输出值并输出非反相信号。

6. 发明授权

US5818306A Voltage control oscillation circuit using CMOS 失效
标题翻译：使用CMOS的电压控制振荡电路
公开(公告)号：US5818306A
公开(公告)日：1998-10-06
申请号：US892938
申请日：1997-07-15
申请人： Jong-Ryul Lee , Ook Kim , Jong-Kee Kwon , Chang-Jun Oh , Won-Chul Song , Kyung-Soo Kim
发明人： Jong-Ryul Lee , Ook Kim , Jong-Kee Kwon , Chang-Jun Oh , Won-Chul Song , Kyung-Soo Kim
IPC分类号： H03B5/00 , H03B1/00 , H03B1/04 , H03B5/12 , H03L5/00
CPC分类号： H03L5/00 , H03B5/1209 , H03B5/1215 , H03B5/1221 , H03B5/1228 , H03B5/1243 , H03B2200/0066 , H03B2200/0082 , H03B2200/0086 , H03B2200/0088 , H03B2200/0098 , H03B2201/0208 , H03B2202/012 , H03B2202/06
摘要： A voltage control oscillation circuit for a CMOS which is capable of reducing phase noise and power consumption by adapting a voltage amplitude control loop and a common mode feedback circuit to a conventional LC-tank circuit. The circuit includes an LC-tank oscillation unit for outputting an oscillation voltage, an output common mode feedback unit for receiving an output from the LC-tank oscillation unit and eliminating a common mode noise of the output, and a voltage amplitude control unit for controlling a bias current of the LC-tank oscillation unit in accordance with a voltage difference at both ends of an LC-tank oscillation terminal which voltage is applied thereto through the output common mode feedback unit, for thus controlling the amount of an oscillation voltage.
摘要翻译：一种用于CMOS的电压控制振荡电路，其能够通过使电压幅度控制回路和共模反馈电路适应于传统的LC槽电路来降低相位噪声和功耗。电路包括用于输出振荡电压的LC槽振荡单元，用于接收来自LC槽振荡单元的输出并消除输出的共模噪声的输出共模反馈单元和用于控制的电压幅度控制单元根据通过输出共模反馈单元向其施加电压的LC槽振荡端子的两端的电压差，LC槽振荡单元的偏置电流，从而控制振荡电压的量。

7. 发明授权

US6121818A Mixer using replica voltage-current converter 失效
标题翻译：混频器使用复制电压电流转换器
公开(公告)号：US6121818A
公开(公告)日：2000-09-19
申请号：US970350
申请日：1997-11-14
申请人： Ook Kim , Jong-Kee Kwon , Jong-Ryul Lee , Chang-Jun Oh , Won-Chul Song
发明人： Ook Kim , Jong-Kee Kwon , Jong-Ryul Lee , Chang-Jun Oh , Won-Chul Song
IPC分类号： H03D7/00 , H03D7/14 , G06F7/44
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D2200/0088
摘要： The present invention discloses a mixer using a replica voltage-current converter, and more particularly a mixer using the replica voltage-current (V-I) converter of the present invention, which feedbacks the output current of the replica voltage-current converter using an additional amplifier so as to improve the linearity thereof by the gain of the amplifier because the conventional mixer operating at a high speed dissipates a lot of electrical power to have low output impedance.
摘要翻译：本发明公开了一种使用复制电压 - 电流转换器的混频器，特别是使用本发明的复制电压 - 电流（VI）转换器的混频器，其使用附加放大器来反馈复制电压 - 电流转换器的输出电流以便通过放大器的增益来提高其线性度，因为常规的混频器以高速度运行，将大量的电能消耗到具有低的输出阻抗。

8. 发明授权

US5880616A Digital logic level conversion circuit with a small sinusodal wave input 失效
标题翻译：数字逻辑电平转换电路具有小的正弦波输入
公开(公告)号：US5880616A
公开(公告)日：1999-03-09
申请号：US769808
申请日：1996-12-18
申请人： Moon Yang Park , Ook Kim , Jong Ryul Lee
发明人： Moon Yang Park , Ook Kim , Jong Ryul Lee
IPC分类号： H03K19/00 , H03K5/08 , H03K5/156 , H03L5/00
CPC分类号： H03K5/086 , H03K5/1565
摘要： The digital logic level conversion circuit is for converting a small sinusoidal signal or an unbalanced digital signal to a balanced digital signal with 50% duty ratio, and includes an input level shift circuit, two differential amplifiers, an RS flip-flop, a charge-pump circuit, and a bias circuit. The input level shift circuit for AC coupling a sinusoidal wave with a small amplitude (with a minimum of 0.4 Vpp) and converting it into a middle logic level. The two differential amplifiers is used as comparators having hysteresis each other, operates inversely, and outputs digital signals into the RS flip-flop; the bias circuit for controlling a driving current of the differential amplifiers; the RS flip-flop for driving the charge-pump circuit by outputting a digital signal upon receiving outputs from the differential amplifiers; and the charge-pump circuit for generating a reference potential level of the differential amplifiers.
摘要翻译：数字逻辑电平转换电路用于将小正弦信号或不平衡数字信号转换成具有50％占空比的平衡数字信号，并且包括输入电平移位电路，两个差分放大器，RS触发器，泵电路和偏置电路。用于交流耦合具有小振幅（至少为0.4 Vpp）的正弦波并将其转换为中间逻辑电平的输入电平移位电路。两个差分放大器用作具有滞后的比较器，反向工作，并将数字信号输出到RS触发器中; 用于控制差分放大器的驱动电流的偏置电路; RS触发器，用于在从差分放大器接收到输出时通过输出数字信号来驱动电荷泵电路; 以及用于产生差分放大器的参考电位电平的电荷泵电路。

9. 发明授权

US07500032B2 Cable with circuitry for asserting stored cable data or other information to an external device or user 有权
标题翻译：电缆，用于断开存储的电缆数据或其他信息到外部设备或用户的电路
公开(公告)号：US07500032B2
公开(公告)日：2009-03-03
申请号：US11848758
申请日：2007-08-31
申请人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Hoon Kim , Gijung Ahn , Seung Ho Hwang
发明人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Hoon Kim , Gijung Ahn , Seung Ho Hwang
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.
摘要翻译：包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。电缆可以包括导体，存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路，并且将所访问的数据串行地认定到至少一个导体（例如，用于传输到外部设备）。本发明的其他方面是用于访问存储在电缆中并且可选地使用数据（例如，实现均衡）的电缆数据的方法。电缆数据可以表示电缆类型，等级，速度，长度和阻抗的全部或一些，日期代码，频率相关衰减表，远端串扰和EMI相关系数，共模辐射，内部对歪斜等信息。电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色，亮度和/或闪烁图案的驱动信号的电路。

10. 发明申请

US20080022023A1 Cable with Circuitry for Asserting Stored Cable Data or Other Information to an External Device or User 有权
标题翻译：电缆用于将存储的电缆数据或其他信息提供给外部设备或用户
公开(公告)号：US20080022023A1
公开(公告)日：2008-01-24
申请号：US11848758
申请日：2007-08-31
申请人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Kim , Gijung Ahn , Seung Hwang
发明人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Kim , Gijung Ahn , Seung Hwang
IPC分类号： G06F13/38 , G06F3/00
CPC分类号： G06F13/385
摘要： A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.
摘要翻译：包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。电缆可以包括导体，存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路，并且将所访问的数据串行地认定到至少一个导体（例如，用于传输到外部设备）。本发明的其他方面是用于访问存储在电缆中并且可选地使用数据（例如，实现均衡）的电缆数据的方法。电缆数据可以表示电缆类型，等级，速度，长度和阻抗的全部或一些，日期代码，频率相关衰减表，远端串扰和EMI相关系数，共模辐射，内部对歪斜等信息。电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色，亮度和/或闪烁图案的驱动信号的电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式