专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06677639B2 Non-volatile memory device and method for fabricating the same 有权
公开(公告)号：US06677639B2
公开(公告)日：2004-01-13
申请号：US10188389
申请日：2002-07-01
申请人： Chang-Hyun Lee , Jung-Dal Choi , Byung-Kwan You , Sung-Hoi Hur
发明人： Chang-Hyun Lee , Jung-Dal Choi , Byung-Kwan You , Sung-Hoi Hur
IPC分类号： H01L2976
CPC分类号： H01L27/11568 , H01L27/115
摘要： A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region. Accordingly, leakage current can be substantially suppressed at the boundary region between the isolation region and the floating region.

2. 发明授权

US06677200B2 Method of forming non-volatile memory having floating trap type device 失效
标题翻译：形成具有浮动陷阱型装置的非易失性存储器的方法
公开(公告)号：US06677200B2
公开(公告)日：2004-01-13
申请号：US10194182
申请日：2002-07-12
申请人： Chang-Hyun Lee , Jung-Dal Choi , Sung-Hoi Hur
发明人： Chang-Hyun Lee , Jung-Dal Choi , Sung-Hoi Hur
IPC分类号： H01L213366
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/66833 , Y10S438/954
摘要： A method of forming a non-volatile memory having a floating trap-type device is disclosed in the present invention. In the method, a relatively thick thermal oxide layer is formed at a semiconductor substrate and patterned to leave a thick thermal oxide pattern at a high-voltage region (a high-voltage region defining step). An oxide-nitride-oxide (ONO) layer is formed over substantially the entire surface (the substantial surface) of the semiconductor substrate and patterned to leave an ONO pattern at a cell memory region (a cell memory region defining step). After the high-voltage region defining step and the cell memory region defining step, a thermal oxidizing process is performed with respect to the semiconductor substrate where a low-voltage region is exposed, thereby forming a relatively thin gate insulation layer for a low-voltage type device (a low-voltage region defining region).
摘要翻译：在本发明中公开了形成具有浮动陷阱型装置的非易失性存储器的方法。在该方法中，在半导体衬底上形成相对较厚的热氧化物层，并将其图案化以在高电压区域（高电压区域限定步骤）处留下厚的热氧化物图案。在半导体衬底的基本上整个表面（基本表面）上形成氧化物 - 氧化物（ONO）层，并将其图案化以在单元存储区（单元存储区定义步骤）处留下ONO图案。在高电压区域定义步骤和电池存储区域限定步骤之后，对于暴露低电压区域的半导体衬底进行热氧化处理，从而形成用于低电压的较薄的栅极绝缘层（低电压区域限定区域）。

3. 发明授权

US06818510B2 Non-volatile memory device and method for fabricating the same 有权
公开(公告)号：US06818510B2
公开(公告)日：2004-11-16
申请号：US10704285
申请日：2003-11-06
申请人： Chang-Hyun Lee , Jung-Dal Choi , Byung-Kwan You , Sung-Hoi Hur
发明人： Chang-Hyun Lee , Jung-Dal Choi , Byung-Kwan You , Sung-Hoi Hur
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region. Accordingly, leakage current can be substantially suppressed at the boundary region between the isolation region and the floating region.

4. 发明授权

US07122426B2 Method of fabricating cell of nonvolatile memory device with floating gate 有权
标题翻译：具有浮动栅极的非易失性存储器件单元制造方法
公开(公告)号：US07122426B2
公开(公告)日：2006-10-17
申请号：US10788002
申请日：2004-02-25
申请人： Chang-Hyun Lee , Kyu-Charn Park , Jeong-Hyuk Choi , Sung-Hoi Hur
发明人： Chang-Hyun Lee , Kyu-Charn Park , Jeong-Hyuk Choi , Sung-Hoi Hur
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , Y10S257/905
摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.
摘要翻译：本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。每个器件隔离层具有突出在半导体衬底上的侧壁。多个字线跨越器件隔离层。隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极顺序堆叠的图案。然后在器件隔离层和控制栅极图案上形成导电层。此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

5. 发明授权

US06903406B2 Cells of nonvolatile memory device with high inter-layer dielectric constant 有权
标题翻译：具有高层间介电常数的非易失性存储器件的单元
公开(公告)号：US06903406B2
公开(公告)日：2005-06-07
申请号：US10346957
申请日：2003-01-17
申请人： Chang-Hyun Lee , Kyu-Charn Park , Jeong-Hyuk Choi , Sung-Hoi Hur
发明人： Chang-Hyun Lee , Kyu-Charn Park , Jeong-Hyuk Choi , Sung-Hoi Hur
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , Y10S257/905
摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.
摘要翻译：本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。每个器件隔离层具有突出在半导体衬底上的侧壁。多个字线跨越器件隔离层。隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极顺序堆叠的图案。然后在器件隔离层和控制栅极图案上形成导电层。此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

6. 发明授权

US07449763B2 Method of fabricating cell of nonvolatile memory device with floating gate 有权
标题翻译：具有浮动栅极的非易失性存储器件单元制造方法
公开(公告)号：US07449763B2
公开(公告)日：2008-11-11
申请号：US11530827
申请日：2006-09-11
申请人： Chang-Hyun Lee , Kyu-Charn Park , Jeong-Hyuk Choi , Sung-Hoi Hur
发明人： Chang-Hyun Lee , Kyu-Charn Park , Jeong-Hyuk Choi , Sung-Hoi Hur
IPC分类号： H01L29/00 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , Y10S257/905
摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.
摘要翻译：本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。每个器件隔离层具有突出在半导体衬底上的侧壁。多个字线跨越器件隔离层。隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极顺序堆叠的图案。然后在器件隔离层和控制栅极图案上形成导电层。此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

7. 发明授权

US08629489B2 Nonvolatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US08629489B2
公开(公告)日：2014-01-14
申请号：US13357350
申请日：2012-01-24
申请人： Chang-Hyun Lee , Jung-Dal Choi
发明人： Chang-Hyun Lee , Jung-Dal Choi
IPC分类号： H01L29/76
CPC分类号： H01L27/1052 , G11C16/0483 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.
摘要翻译：非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

8. 发明申请

US20110079838A1 NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：US20110079838A1
公开(公告)日：2011-04-07
申请号：US12961678
申请日：2010-12-07
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/1157 , H01L27/11524 , H01L27/11551 , H01L27/11578 , H01L29/42352 , H01L29/7851 , H01L29/792
摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.
摘要翻译：一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极在栅极结构的相对侧的有源区中的区域。源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。还讨论了相关设备。

9. 发明授权

US07864582B2 Nonvolatile memory devices and methods of operating same to inhibit parasitic charge accumulation therein 有权
标题翻译：非易失性存储器件及其操作方法，以抑制其中的寄生电荷积聚
公开(公告)号：US07864582B2
公开(公告)日：2011-01-04
申请号：US12191434
申请日：2008-08-14
申请人： Chang-Hyun Lee , Jung-Dal Choi , Young-Ho Lim , Kang-Deog Suh
发明人： Chang-Hyun Lee , Jung-Dal Choi , Young-Ho Lim , Kang-Deog Suh
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/16
摘要： Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells.
摘要翻译：操作电荷阱非易失性存储装置的方法包括通过选择性地擦除第一串中的第一多个非易失性存储单元，然后选择性地擦除第一串中的第二多个非易失性存储单元来擦除第一串非易失性存储单元的操作，其可以与第一多个非易失性存储器单元交错。选择性地擦除第一多个非易失性存储单元的操作可以包括擦除第一多个非易失性存储单元，同时在禁止擦除第二多个非易失性存储单元的阻塞条件下同时偏置第二多个非易失性存储单元。选择性地擦除第二多个非易失性存储单元的操作可以包括擦除第二多个非易失性存储单元，同时在禁止擦除第一多个非易失性存储单元的阻塞条件下同时偏置第一多个非易失性存储单元。

10. 发明申请

US20100327371A1 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20100327371A1
公开(公告)日：2010-12-30
申请号：US12805962
申请日：2010-08-26
申请人： Chang-Hyun Lee , Jung-dal Choi
发明人： Chang-Hyun Lee , Jung-dal Choi
IPC分类号： H01L27/088 , H01L21/8239
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.
摘要翻译：一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域晶体管是第一类型。第一种类型可以是n型或p型。非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式