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1. 发明授权

US09166020B2 Metal gate structure and manufacturing method thereof 有权
标题翻译：金属门结构及其制造方法
公开(公告)号：US09166020B2
公开(公告)日：2015-10-20
申请号：US13037383
申请日：2011-03-01
申请人： Chan-Lon Yang , Chi-Mao Hsu , Chun-Yuan Wu , Tzyy-Ming Cheng , Shih-Fang Tzou , Chin-Fu Lin , Hsin-Fu Huang , Min-Chuan Tsai
发明人： Chan-Lon Yang , Chi-Mao Hsu , Chun-Yuan Wu , Tzyy-Ming Cheng , Shih-Fang Tzou , Chin-Fu Lin , Hsin-Fu Huang , Min-Chuan Tsai
IPC分类号： H01L29/78 , H01L21/28 , H01L29/66 , H01L29/49 , H01L29/51 , H01L29/165
CPC分类号： H01L29/517 , H01L21/28088 , H01L29/165 , H01L29/42364 , H01L29/42376 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843
摘要： A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.
摘要翻译：一种金属栅极结构的制造方法，其特征在于，具备在其上依次形成有高K栅极电介质层和底部阻挡层的基板，在基板上形成功函数金属层，对功函数金属层进行退火处理原位。

2. 发明申请

US20120223397A1 METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：金属门结构及其制造方法
公开(公告)号：US20120223397A1
公开(公告)日：2012-09-06
申请号：US13037383
申请日：2011-03-01
申请人： Chan-Lon Yang , Chi-Mao Hsu , Chun-Yuan Wu , Tzyy-Ming Cheng , Shih-Fang Tzou , Chin-Fu Lin , Hsin-Fu Huang , Min-Chuan Tsai
发明人： Chan-Lon Yang , Chi-Mao Hsu , Chun-Yuan Wu , Tzyy-Ming Cheng , Shih-Fang Tzou , Chin-Fu Lin , Hsin-Fu Huang , Min-Chuan Tsai
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/517 , H01L21/28088 , H01L29/165 , H01L29/42364 , H01L29/42376 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843
摘要： A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.
摘要翻译：一种金属栅极结构的制造方法，其特征在于，具备在其上依次形成有高K栅极电介质层和底部阻挡层的基板，在基板上形成功函数金属层，对功函数金属层进行退火处理原位。

3. 发明申请

US20120086054A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120086054A1
公开(公告)日：2012-04-12
申请号：US12902159
申请日：2010-10-12
申请人： Tzyy-Ming Cheng , Meng-Chi Tsai , Tsai-Fu Chen , Ta-Kang Lo , Wen-Han Hung , Shih-Fang Tzou , Chun-Yuan Wu
发明人： Tzyy-Ming Cheng , Meng-Chi Tsai , Tsai-Fu Chen , Ta-Kang Lo , Wen-Han Hung , Shih-Fang Tzou , Chun-Yuan Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L23/485 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a gate structure disposed on a substrate, a source and a drain respectively disposed in the substrate at two sides of the gate structure, a source contact plug disposed above the source and electrically connected to the source and a drain contact plug disposed above the drain and electrically connected to the drain. The source contact plug and the drain contact plug have relatively asymmetric element properties.
摘要翻译：公开了半导体结构。半导体结构包括设置在基板上的栅极结构，在栅极结构的两侧分别设置在基板中的源极和漏极，设置在源极上并电连接到源极的源极接触插塞和设置在漏极接触插塞在漏极上方并与漏极电连接。源极接触插塞和漏极接触插塞具有相对不对称的元件特性。

4. 发明申请

US20120070948A1 ADJUSTING METHOD OF CHANNEL STRESS 审中-公开
标题翻译：通道应力调整方法
公开(公告)号：US20120070948A1
公开(公告)日：2012-03-22
申请号：US12883266
申请日：2010-09-16
申请人： Tzyy-Ming CHENG , Ching-Sen Lu , Tsai-Fu Chen , Wen-Han Hung , Ta-Kang Lo , Chun-Yuan Wu , Shih-Fang Tzou
发明人： Tzyy-Ming CHENG , Ching-Sen Lu , Tsai-Fu Chen , Wen-Han Hung , Ta-Kang Lo , Chun-Yuan Wu , Shih-Fang Tzou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/823412
摘要： An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region.
摘要翻译：通道应力调整方法包括以下步骤。提供基板。在基板上形成金属氧化物半导体场效应晶体管。 MOSFET包括源极/漏极区域，沟道，栅极，栅极介电层和间隔物。在基板上形成电介质层并覆盖金属氧化物半导体场效应晶体管。将平坦化工艺施加到电介质层上。去除剩余的介电层以暴露源/漏区。在具有暴露的源极/漏极区域的衬底上形成非共形高应力介电层。

5. 发明授权

US08329597B2 Semiconductor process having dielectric layer including metal oxide and MOS transistor process 有权
标题翻译：具有包括金属氧化物和MOS晶体管工艺的电介质层的半导体工艺
公开(公告)号：US08329597B2
公开(公告)日：2012-12-11
申请号：US13041451
申请日：2011-03-07
申请人： Chan-Lon Yang , Shih-Fang Tzou , Chen-Kuo Chiang
发明人： Chan-Lon Yang , Shih-Fang Tzou , Chen-Kuo Chiang
IPC分类号： H01L21/31
CPC分类号： H01L21/28185 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor process having a dielectric layer including metal oxide is provided. The semiconductor process includes: A substrate is provided. A dielectric layer including metal oxide is formed on the substrate, wherein the dielectric layer has a plurality of oxygen-related vacancies. A first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen. Otherwise, three MOS transistor processes are also provided, each of which has a gate dielectric layer including a high dielectric constant, and a first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen.
摘要翻译：提供了具有包括金属氧化物的电介质层的半导体工艺。半导体工艺包括：提供衬底。在基板上形成包括金属氧化物的电介质层，其中介电层具有多个与氧有关的空位。进行第一氧气进入处理以用氧填充与氧相关的空位。另外，还提供三个MOS晶体管工艺，每个MOS晶体管工艺都具有包括高介电常数的栅极电介质层，并且执行第一氧气进入工艺以用氧填充与氧相关的空位。

6. 发明申请

US20120231600A1 SEMICONDUCTOR PROCESS HAVING DIELECTRIC LAYER INCLUDING METAL OXIDE AND MOS TRANSISTOR PROCESS 有权
标题翻译：具有包含金属氧化物和MOS晶体管工艺的介电层的半导体工艺
公开(公告)号：US20120231600A1
公开(公告)日：2012-09-13
申请号：US13041451
申请日：2011-03-07
申请人： Chan-Lon Yang , Shih-Fang Tzou , Chen-Kuo Chiang
发明人： Chan-Lon Yang , Shih-Fang Tzou , Chen-Kuo Chiang
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/28185 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor process having a dielectric layer including metal oxide is provided. The semiconductor process includes: A substrate is provided. A dielectric layer including metal oxide is formed on the substrate, wherein the dielectric layer has a plurality of oxygen-related vacancies. A first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen. Otherwise, three MOS transistor processes are also provided, each of which has a gate dielectric layer including a high dielectric constant, and a first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen.
摘要翻译：提供了具有包括金属氧化物的电介质层的半导体工艺。半导体工艺包括：提供衬底。在基板上形成包括金属氧化物的电介质层，其中介电层具有多个与氧有关的空位。进行第一氧气进入处理以用氧填充与氧相关的空位。另外，还提供三个MOS晶体管工艺，每个MOS晶体管工艺都具有包括高介电常数的栅极电介质层，并且执行第一氧气进入工艺以用氧填充与氧相关的空位。

7. 发明申请

US20100105205A1 CLEANING SOLUTION AND SEMICONDCUTOR PROCESS USING THE SAME 审中-公开
标题翻译：使用相同的清洁溶液和半导体工艺
公开(公告)号：US20100105205A1
公开(公告)日：2010-04-29
申请号：US12259033
申请日：2008-10-27
申请人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L21/44 , C11D3/28
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/3281 , H01L21/02063 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water.
摘要翻译：提供半导体工艺。首先，在基板上依次形成金属层，电介质层和图案化的硬掩模层。此后，去除介电层的一部分以形成露出金属层的开口。之后，使用清洁溶液清洁开口。清洗液含有含量为0.00275〜3重量％的三唑化合物，含量为1〜10重量％的硫酸，含量为1〜200ppm的氢氟酸和水。

8. 发明申请

US20080064176A1 Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device 有权
标题翻译：去除间隔物的方法，制造金属氧化物半导体晶体管器件的方法和金属氧化物半导体晶体管器件
公开(公告)号：US20080064176A1
公开(公告)日：2008-03-13
申请号：US11531260
申请日：2006-09-12
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.
摘要翻译：一种去除间隔物的方法，制造金属氧化物半导体晶体管器件的方法和金属氧化物半导体晶体管器件，其中在去除间隔物之前，保护层沉积在间隔物上形成在源极/漏极区域上的材料层（例如自对准硅化物层）和栅电极，使得隔离物上的保护层的厚度小于材料层上的厚度，然后保护层部分去除，使得隔离物上的保护层的厚度近似为零，并且保护层的一部分保留在材料层上。因此，当去除间隔物时，材料层可被保护层保护。

9. 发明申请

US20070238238A1 CMOS device and fabricating method thereof 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US20070238238A1
公开(公告)日：2007-10-11
申请号：US11389617
申请日：2006-03-24
申请人： Shih-Wei Sun , Shih-Fang Tzou , Jiunn-Hsiung Liao , Pei-Yu Chou
发明人： Shih-Wei Sun , Shih-Fang Tzou , Jiunn-Hsiung Liao , Pei-Yu Chou
IPC分类号： H01L21/8238 , H01L29/80
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/7843
摘要： A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation structure. Further, the first-type MOS transistor is disposed on the first active area of the substrate, and the second-type MOS transistor is disposed on the second active area of the substrate. The first stress layer is compliantly disposed on the first-type MOS transistor of the first active area. The first liner layer is compliantly disposed on the first stress layer. The second stress layer is compliantly disposed on the second-type MOS transistor of the second active area.
摘要翻译：提供一种CMOS器件，包括衬底，第一类型MOS晶体管，第二类型MOS晶体管，第一应力层，第一衬里层和第二应力层。衬底具有由隔离结构隔开的第一有源区和第二有源区。此外，第一型MOS晶体管设置在衬底的第一有源区上，并且第二型MOS晶体管设置在衬底的第二有源区上。第一应力层顺应地设置在第一有源区的第一型MOS晶体管上。第一衬里层顺应地设置在第一应力层上。第二应力层顺从地设置在第二有源区的第二型MOS晶体管上。

10. 发明申请

US20080191287A1 METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR 有权
标题翻译：制备应变硅CMOS晶体管的方法
公开(公告)号：US20080191287A1
公开(公告)日：2008-08-14
申请号：US11674660
申请日：2007-02-13
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.
摘要翻译：首先，提供具有第一有源区和第二有源区的半导体基板。第一有源区包括第一晶体管，第二有源区包括第二晶体管。第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

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