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1. 发明申请

US20120086054A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120086054A1
公开(公告)日：2012-04-12
申请号：US12902159
申请日：2010-10-12
申请人： Tzyy-Ming Cheng , Meng-Chi Tsai , Tsai-Fu Chen , Ta-Kang Lo , Wen-Han Hung , Shih-Fang Tzou , Chun-Yuan Wu
发明人： Tzyy-Ming Cheng , Meng-Chi Tsai , Tsai-Fu Chen , Ta-Kang Lo , Wen-Han Hung , Shih-Fang Tzou , Chun-Yuan Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L23/485 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a gate structure disposed on a substrate, a source and a drain respectively disposed in the substrate at two sides of the gate structure, a source contact plug disposed above the source and electrically connected to the source and a drain contact plug disposed above the drain and electrically connected to the drain. The source contact plug and the drain contact plug have relatively asymmetric element properties.
摘要翻译：公开了半导体结构。半导体结构包括设置在基板上的栅极结构，在栅极结构的两侧分别设置在基板中的源极和漏极，设置在源极上并电连接到源极的源极接触插塞和设置在漏极接触插塞在漏极上方并与漏极电连接。源极接触插塞和漏极接触插塞具有相对不对称的元件特性。

2. 发明申请

US20120070948A1 ADJUSTING METHOD OF CHANNEL STRESS 审中-公开
标题翻译：通道应力调整方法
公开(公告)号：US20120070948A1
公开(公告)日：2012-03-22
申请号：US12883266
申请日：2010-09-16
申请人： Tzyy-Ming CHENG , Ching-Sen Lu , Tsai-Fu Chen , Wen-Han Hung , Ta-Kang Lo , Chun-Yuan Wu , Shih-Fang Tzou
发明人： Tzyy-Ming CHENG , Ching-Sen Lu , Tsai-Fu Chen , Wen-Han Hung , Ta-Kang Lo , Chun-Yuan Wu , Shih-Fang Tzou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/823412
摘要： An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region.
摘要翻译：通道应力调整方法包括以下步骤。提供基板。在基板上形成金属氧化物半导体场效应晶体管。 MOSFET包括源极/漏极区域，沟道，栅极，栅极介电层和间隔物。在基板上形成电介质层并覆盖金属氧化物半导体场效应晶体管。将平坦化工艺施加到电介质层上。去除剩余的介电层以暴露源/漏区。在具有暴露的源极/漏极区域的衬底上形成非共形高应力介电层。

3. 发明授权

US08765561B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08765561B2
公开(公告)日：2014-07-01
申请号：US13154396
申请日：2011-06-06
申请人： Wen-Han Hung , Tsai-Fu Chen , Ta-Kang Lo , Tzyy-Ming Cheng
发明人： Wen-Han Hung , Tsai-Fu Chen , Ta-Kang Lo , Tzyy-Ming Cheng
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/324 , H01L29/165 , H01L29/6656 , H01L29/7848
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供衬底; 在基板上形成虚拟栅极; 在所述伪栅极和所述衬底上形成接触蚀刻停止层; 执行平面化处理以部分地去除接触蚀刻停止层; 部分去除虚拟门; 并对接触蚀刻停止层进行热处理。

4. 发明授权

US08404533B2 Metal gate transistor and method for fabricating the same 有权
标题翻译：金属栅极晶体管及其制造方法
公开(公告)号：US08404533B2
公开(公告)日：2013-03-26
申请号：US12860939
申请日：2010-08-23
申请人： Cheng-Yu Ma , Wen-Han Hung , Ta-Kang Lo , Tsai-Fu Chen , Tzyy-Ming Cheng
发明人： Cheng-Yu Ma , Wen-Han Hung , Ta-Kang Lo , Tsai-Fu Chen , Tzyy-Ming Cheng
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.
摘要翻译：公开了一种用于制造金属栅极晶体管的方法。该方法包括以下步骤：提供衬底，其中衬底包括限定在其上的晶体管区域; 在所述基板上形成栅极绝缘层; 在所述栅绝缘层上形成层叠膜，其中所述层叠膜包括至少一个蚀刻停止层，多晶硅层和硬掩模; 图案化栅极绝缘层和用于在基板上形成伪栅极的叠层膜; 在所述虚拟栅极上形成介电层; 执行用于部分去除电介质层直到到达虚拟栅极的顶部的平坦化处理; 去除虚拟栅极的多晶硅层; 去除用于形成开口的虚拟栅极的蚀刻停止层; 以及在用于形成栅极的开口中形成导电层。

5. 发明申请

US20120199890A1 TRANSISTOR STRUCTURE 有权
标题翻译：晶体管结构
公开(公告)号：US20120199890A1
公开(公告)日：2012-08-09
申请号：US13450444
申请日：2012-04-18
申请人： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
发明人： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
IPC分类号： H01L29/78
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7848
摘要： A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.
摘要翻译：在本发明中提供一种晶体管结构。晶体管结构包括：包括P型阱的衬底，设置在P型阱上的栅极，设置在栅极上的第一间隔物，设置在栅极两侧的衬底中的N型源极/漏极区域覆盖N型源极/漏极区域的硅覆盖层，围绕第一间隔物的第二间隔物和第二间隔物，直接覆盖硅覆盖层的一部分并且覆盖硅覆盖层上的硅化物层。

6. 发明授权

US08486795B2 Method of fabricating transistors 有权
标题翻译：制造晶体管的方法
公开(公告)号：US08486795B2
公开(公告)日：2013-07-16
申请号：US13444855
申请日：2012-04-12
申请人： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
发明人： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7848
摘要： A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.
摘要翻译：制造晶体管的方法包括：提供包括N型阱和P型阱的衬底; 在N型阱上分别形成第一栅极和P型阱上的第二栅极; 在所述第一门上形成第三间隔物; 在第一栅极的两侧在衬底中形成外延层; 在所述第二闸门上形成第四间隔物; 在所述第四间隔物的两侧形成覆盖所述外延层的表面和所述基板的表面的硅覆盖层; 以及分别在第一栅极和第二栅极的两侧形成第一源极/漏极掺杂区域和第二源极/漏极掺杂区域。

7. 发明申请

US20120309158A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120309158A1
公开(公告)日：2012-12-06
申请号：US13154396
申请日：2011-06-06
申请人： Wen-Han Hung , Tsai-Fu Chen , Ta-Kang Lo , Tzyy-Ming Cheng
发明人： Wen-Han Hung , Tsai-Fu Chen , Ta-Kang Lo , Tzyy-Ming Cheng
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/324 , H01L29/165 , H01L29/6656 , H01L29/7848
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供衬底; 在基板上形成虚拟栅极; 在所述伪栅极和所述衬底上形成接触蚀刻停止层; 执行平面化处理以部分地去除接触蚀刻停止层; 部分去除虚拟门; 并对接触蚀刻停止层进行热处理。

8. 发明授权

US08211775B1 Method of making transistor having metal gate 有权
标题翻译：制造具有金属栅极的晶体管的方法
公开(公告)号：US08211775B1
公开(公告)日：2012-07-03
申请号：US13043479
申请日：2011-03-09
申请人： Cheng-Yu Ma , Wen-Han Hung , Ta-Kang Lo , Tsai-Fu Chen , Tzyy-Ming Cheng
发明人： Cheng-Yu Ma , Wen-Han Hung , Ta-Kang Lo , Tsai-Fu Chen , Tzyy-Ming Cheng
IPC分类号： H01L21/336
CPC分类号： H01L29/66553 , H01L29/4983 , H01L29/513 , H01L29/6656
摘要： A method for forming a transistor having a metal gate is provided. A substrate is provided first. A transistor is formed on the substrate. The transistor includes a high-k gate dielectric layer, an oxygen containing dielectric layer disposed on the high-k gate dielectric layer, and a dummy gate disposed on the oxygen containing dielectric layer. Then, the dummy gate and the patterned gate dielectric layer are removed. Lastly, a metal gate is formed and the metal gate directly contacts the high-k gate oxide.
摘要翻译：提供一种形成具有金属栅极的晶体管的方法。首先提供基板。在基板上形成晶体管。晶体管包括高k栅极电介质层，设置在高k栅极电介质层上的含氧电介质层和设置在含氧电介质层上的伪栅极。然后，去除伪栅极和图案化栅极电介质层。最后，形成金属栅极，并且金属栅极直接接触高k栅极氧化物。

9. 发明授权

US08390073B2 Transistor structure 有权
标题翻译：晶体管结构
公开(公告)号：US08390073B2
公开(公告)日：2013-03-05
申请号：US13450444
申请日：2012-04-18
申请人： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
发明人： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7848
摘要： A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.
摘要翻译：在本发明中提供一种晶体管结构。晶体管结构包括：包括P型阱的衬底，设置在P型阱上的栅极，设置在栅极上的第一间隔物，设置在栅极两侧的衬底中的N型源极/漏极区域覆盖N型源极/漏极区域的硅覆盖层，围绕第一间隔物的第二间隔物和第二间隔物，直接覆盖硅覆盖层的一部分并且覆盖硅覆盖层上的硅化物层。

10. 发明授权

US08183640B2 Method of fabricating transistors and a transistor structure for improving short channel effect and drain induced barrier lowering 有权
标题翻译：制造晶体管的方法和用于改善短沟道效应和漏极引起的屏障降低的晶体管结构
公开(公告)号：US08183640B2
公开(公告)日：2012-05-22
申请号：US12502239
申请日：2009-07-14
申请人： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
发明人： Wen-Han Hung , Tsai-Fu Chen , Shyh-Fann Ting , Cheng-Tung Huang , Kun-Hsien Lee , Ta-Kang Lo , Tzyy-Ming Cheng
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/7848
摘要： A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.
摘要翻译：制造晶体管的方法包括：提供包括N型阱和P型阱的衬底; 在N型阱上分别形成第一栅极和P型阱上的第二栅极; 在所述第一门上形成第三间隔物; 在第一栅极的两侧在衬底中形成外延层; 在所述第二闸门上形成第四间隔物; 在所述第四间隔物的两侧形成覆盖所述外延层的表面和所述基板的表面的硅覆盖层; 以及分别在所述第一栅极和所述第二栅极的两侧形成第一源极/漏极掺杂区域和第二源极/漏极掺杂区域。

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