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1. 发明申请

US20120079232A1 APPARATUS, METHOD, AND SYSTEM FOR IMPLEMENTING MICRO PAGE TABLES 有权
标题翻译：用于实施微型表格的装置，方法和系统
公开(公告)号：US20120079232A1
公开(公告)日：2012-03-29
申请号：US12890585
申请日：2010-09-24
申请人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
发明人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F12/06 , G06F12/1009 , G06F2212/1028 , G06F2212/1041 , G06F2212/151 , G06F2212/205 , G06F2212/651 , Y02D10/13
摘要： An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.
摘要翻译：公开了一种装置，方法，机器可读介质和系统。在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。微页表引擎允许TLB作为一个代理，确定二级存储器层次结构中的数据是在存储器的热区域还是在存储器的冷区域。当数据处于存储器的冷区域时，微页表引擎将数据读取到热存储器，然后将热存储器块推出到冷存储器区域。

2. 发明授权

US08838935B2 Apparatus, method, and system for implementing micro page tables 有权
标题翻译：用于实现微页表的装置，方法和系统
公开(公告)号：US08838935B2
公开(公告)日：2014-09-16
申请号：US12890585
申请日：2010-09-24
申请人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
发明人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
IPC分类号： G06F12/00 , G06F12/10 , G06F12/02
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F12/06 , G06F12/1009 , G06F2212/1028 , G06F2212/1041 , G06F2212/151 , G06F2212/205 , G06F2212/651 , Y02D10/13
摘要： In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.
摘要翻译：在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。

3. 发明授权

US08423682B2 Address space emulation 有权
标题翻译：地址空间仿真
公开(公告)号：US08423682B2
公开(公告)日：2013-04-16
申请号：US11323465
申请日：2005-12-30
申请人： Sham M. Datta , Robert Greiner , Frank Binns , Keshavan Tiruvallur , Rajesh Parthasarathy , Madhavan Parthasarathy
发明人： Sham M. Datta , Robert Greiner , Frank Binns , Keshavan Tiruvallur , Rajesh Parthasarathy , Madhavan Parthasarathy
IPC分类号： G06F3/00 , G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F9/342 , G06F9/30174 , G06F12/0292 , G06F12/063 , G06F2212/206
摘要： Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.
摘要翻译：装置和系统以及方法和物品可以操作以检测与配置存储器地址和第一存储器地址位大小相关联的输入/输出访问操作。配置存储器地址和相关联的配置数据可以被组合成具有大于第一存储器地址位大小（例如，32位）的第二存储器地址位大小（例如，64位）的分组。该分组可以用于为尝试与外围组件互连（PCI）接口的外围设备以及已经集成到与处理器相同的封装中的类似的平台设备进行通信的传统操作系统建立兼容性。

4. 发明申请

US20070174587A1 Address space emulation 有权
标题翻译：地址空间仿真
公开(公告)号：US20070174587A1
公开(公告)日：2007-07-26
申请号：US11323465
申请日：2005-12-30
申请人： Sham Datta , Robert Greiner , Frank Binns , Keshavan Tiruvallur , Rajesh Parthasarathy , Madhavan Parthasarathy
发明人： Sham Datta , Robert Greiner , Frank Binns , Keshavan Tiruvallur , Rajesh Parthasarathy , Madhavan Parthasarathy
IPC分类号： G06F15/00
CPC分类号： G06F9/342 , G06F9/30174 , G06F12/0292 , G06F12/063 , G06F2212/206
摘要： Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.
摘要翻译：装置和系统以及方法和物品可以操作以检测与配置存储器地址和第一存储器地址位大小相关联的输入/输出访问操作。配置存储器地址和相关联的配置数据可以被组合成具有大于第一存储器地址位大小（例如，32位）的第二存储器地址位大小（例如，64位）的分组。该分组可以用于为尝试与外围组件互连（PCI）接口的外围设备以及已经集成到与处理器相同的封装中的类似的平台设备进行通信的传统操作系统建立兼容性。

5. 发明授权

US08738889B2 Generating multiple address space identifiers per virtual machine to switch between protected micro-contexts 有权
标题翻译：为每个虚拟机生成多个地址空间标识符，以便在受保护的微上下文之间切换
公开(公告)号：US08738889B2
公开(公告)日：2014-05-27
申请号：US13650227
申请日：2012-10-12
申请人： Uday Savagaonkar , Madhavan Parthasarathy , Ravi Sahita , David Durham
发明人： Uday Savagaonkar , Madhavan Parthasarathy , Ravi Sahita , David Durham
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/145
摘要： Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, a method includes receiving an instruction requiring an address translation; initiating, in response to receiving the instruction, a page walk from a page table pointed to by the contents of a page table pointer storage location; finding, during the page walk, a transition entry; storing the address translation and one of a plurality of address source identifiers in a translation lookaside buffer, the one of the plurality of address source identifiers based on one of a plurality of a virtual partition identifiers, at least two of the plurality of virtual partition identifiers associated with one of a plurality of virtual machines; and re-initiating the page walk.
摘要翻译：公开了用于在每个虚拟机之间生成多个地址空间标识符以在受保护的微上下文之间切换的发明的实施例。在一个实施例中，一种方法包括接收需要地址转换的指令; 响应于接收到指令，从页表指针存储位置的内容指向的页表中启动页面移动; 在页面散步期间发现转换条目; 将地址转换和多个地址源标识符之一存储在转换后备缓冲器中，所述多个地址源标识符中的一个基于多个虚拟分区标识符中的一个，多个虚拟分区标识符中的至少两个与多个虚拟机中的一个相关联; 并重新启动页面散步。

6. 发明申请

US20130036291A1 GENERATING MULTIPLE ADDRESS SPACE IDENTIFIERS PER VIRTUAL MACHINE TO SWITCH BETWEEN PROTECTED MICRO-CONTEXTS 有权
标题翻译：每个虚拟机产生多个地址空间识别器，以保护受保护的微控制器
公开(公告)号：US20130036291A1
公开(公告)日：2013-02-07
申请号：US13650227
申请日：2012-10-12
申请人： Uday Savagaonkar , Madhavan Parthasarathy , Ravi Sahita , David Durham
发明人： Uday Savagaonkar , Madhavan Parthasarathy , Ravi Sahita , David Durham
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/145
摘要： Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, a method includes receiving an instruction requiring an address translation; initiating, in response to receiving the instruction, a page walk from a page table pointed to by the contents of a page table pointer storage location; finding, during the page walk, a transition entry; storing the address translation and one of a plurality of address source identifiers in a translation lookaside buffer, the one of the plurality of address source identifiers based on one of a plurality of a virtual partition identifiers, at least two of the plurality of virtual partition identifiers associated with one of a plurality of virtual machines; and re-initiating the page walk.
摘要翻译：公开了用于在每个虚拟机之间生成多个地址空间标识符以在受保护的微上下文之间切换的发明的实施例。在一个实施例中，一种方法包括接收需要地址转换的指令; 响应于接收到指令，从页表指针存储位置的内容指向的页表中启动页面移动; 在页面散步期间发现转换条目; 将地址转换和多个地址源标识符之一存储在转换后备缓冲器中，所述多个地址源标识符中的一个基于多个虚拟分区标识符中的一个，多个虚拟分区标识符中的至少两个与多个虚拟机中的一个相关联; 并重新启动页面散步。

7. 发明授权

US08316211B2 Generating multiple address space identifiers per virtual machine to switch between protected micro-contexts 失效
标题翻译：为每个虚拟机生成多个地址空间标识符，以便在受保护的微上下文之间切换
公开(公告)号：US08316211B2
公开(公告)日：2012-11-20
申请号：US12165640
申请日：2008-06-30
申请人： Uday Savagaonkar , Madhavan Parthasarathy , Ravi Sahita , David Durham
发明人： Uday Savagaonkar , Madhavan Parthasarathy , Ravi Sahita , David Durham
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/145
摘要： Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, an apparatus includes privileged mode logic, an interface, and memory management logic. The privileged mode logic is to transfer control of the processor among a plurality of virtual machines. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address. The determination logic is to determine whether an entry is storing an address of a different data structure for the first translation stage. The translation lookaside buffer is to store translations. Each translation lookaside buffer entry includes an address source identifiers. Each address source identifier is to identify a unique micro-context. Each address source identifier is based on a virtual partition identifier. At least two of the of virtual partition identifiers are associated with one of the virtual machines.
摘要翻译：公开了用于在每个虚拟机之间生成多个地址空间标识符以在受保护的微上下文之间切换的发明的实施例。在一个实施例中，装置包括特权模式逻辑，接口和存储器管理逻辑。特权模式逻辑是在多个虚拟机之间传送处理器的控制。该接口是执行一个事务来从内存中获取信息。存储器管理逻辑将非翻译地址转换为存储器地址。存储器管理逻辑包括存储位置，一系列翻译级，确定逻辑和翻译后备缓冲器。存储位置是存储用于第一翻译阶段的数据结构的地址。每个翻译阶段包括翻译逻辑，以基于未翻译地址的一部分在数据结构中找到条目。每个条目是存储用于第一翻译阶段的不同数据结构的地址，用于连续翻译阶段的数据结构的地址或物理地址。确定逻辑是确定条目是否存储用于第一翻译阶段的不同数据结构的地址。翻译后备缓冲区用于存储翻译。每个翻译后备缓冲器条目包括地址源标识符。每个地址源标识符是识别唯一的微观上下文。每个地址源标识符都是基于虚拟分区标识符。至少两个虚拟分区标识符与一个虚拟机相关联。

8. 发明授权

US06708269B1 Method and apparatus for multi-mode fencing in a microprocessor system 有权
标题翻译：微处理器系统中多模式击剑的方法和装置
公开(公告)号：US06708269B1
公开(公告)日：2004-03-16
申请号：US09475098
申请日：1999-12-30
申请人： Keshavan K. Tiruvallur , Douglas M. Carmean , Robert J. Greiner , Muntaquim Chowdhury , Madhavan Parthasarathy
发明人： Keshavan K. Tiruvallur , Douglas M. Carmean , Robert J. Greiner , Muntaquim Chowdhury , Madhavan Parthasarathy
IPC分类号： G06F9312
CPC分类号： G06F9/3824 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3842 , G06F9/3851
摘要： In a multi-threaded system, such as in a multi-processor system, different types of fences are provided to force completion of programmatically earlier instructions in a program. The types of fences can be thread-specific, and different types of fences are used based on different kinds of conditions, instructions, operations, or memory types. When a fence is executed, senior stores, request buffers, bus queues, or any combination of these stages in an execution pipeline can be drained. Fetches at a front end of the pipeline can also be killed to ensure that the bus queue can be drained.
摘要翻译：在多线程系统中，例如在多处理器系统中，提供了不同类型的围栏，以强制程序化程序中早期指令的完成。栅栏的类型可以是线程特定的，并且基于不同种类的条件，指令，操作或存储器类型使用不同类型的栅栏。执行栅栏时，执行管道中的高级存储，请求缓冲区，总线队列或这些阶段的任意组合可能会被排除。管道前端的汲取也可能被杀死，以确保总线队列可以排空。

9. 发明申请

US20150121366A1 VIRTUALIZATION EXCEPTIONS 有权
标题翻译：虚拟化例外
公开(公告)号：US20150121366A1
公开(公告)日：2015-04-30
申请号：US14064759
申请日：2013-10-28
申请人： Gilbert Neiger , Mayank Bomb , Manohar Castelino , Robert Chappell , David Durham , Barry Huntley , Anton Ivanov , Madhavan Parthasarathy , Scott Rodgers , Ravi Sahita , Vedvyas Shanbhogue
发明人： Gilbert Neiger , Mayank Bomb , Manohar Castelino , Robert Chappell , David Durham , Barry Huntley , Anton Ivanov , Madhavan Parthasarathy , Scott Rodgers , Ravi Sahita , Vedvyas Shanbhogue
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F9/30076 , G06F9/45533 , G06F9/4555 , G06F9/4812 , G06F11/07 , G06F2009/45583
摘要： Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.
摘要翻译：公开了用于虚拟化异常的发明的实施例。在一个实施例中，处理器包括指令硬件，控制逻辑和执行硬件。指令硬件是接收多个指令，包括进入虚拟机的指令。控制逻辑是为了响应在虚拟机内发生的特权事件来确定是否生成虚拟化异常。执行硬件是响应于控制逻辑确定生成虚拟化异常来生成虚拟化异常。

10. 发明授权

US07100029B2 Performing repeat string operations 有权
标题翻译：执行重复字符串操作
公开(公告)号：US07100029B2
公开(公告)日：2006-08-29
申请号：US10233155
申请日：2002-08-28
申请人： Xiang Zou , Rajesh S. Parthasarathy , Madhavan Parthasarathy , Dion Rodgers
发明人： Xiang Zou , Rajesh S. Parthasarathy , Madhavan Parthasarathy , Dion Rodgers
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3824 , G06F9/30018 , G06F9/30043 , G06F9/325
摘要： Performing repeat string operations can include aligning a source data location or a destination data location to a location divisible by a predetermined integer, the aligning including performing a string operation using data having a size equal to the operand size. After aligning, a string operation can be performed using data having a size larger than the operand size. Performing repeat string operations can include issuing a first predetermined number of iterations if an operand size is a predetermined size, and issuing a second predetermined number of iterations otherwise. Performing repeat string operations can include determining that a requested number of iterations in a repeat string operation is within a predetermined multi-number range and issuing exactly the requested number of iterations for any value of the requested number within that range.
摘要翻译：执行重复串操作可以包括将源数据位置或目的地数据位置对准可被预定整数整除的位置，所述对齐包括使用具有等于操作数大小的大小的数据来执行字符串操作。对齐后，可以使用尺寸大于操作数大小的数据来执行字符串操作。执行重复字符串操作可以包括：如果操作数大小是预定大小，则发出第一预定数量的迭代，否则发出第二预定次数的迭代。执行重复字符串操作可以包括确定重复字符串操作中所请求的迭代次数在预定的多数量级范围内，并且对该范围内的请求号码的任何值准确地发出所请求的迭代次数。

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