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1. 发明授权

US07498213B2 Methods of fabricating a semiconductor substrate for reducing wafer warpage 失效
标题翻译：制造半导体衬底以减少晶片翘曲的方法
公开(公告)号：US07498213B2
公开(公告)日：2009-03-03
申请号：US11530218
申请日：2006-09-08
申请人： Won-Jin Kim , Young-Wook Park , Jeong-Do Ryu
发明人： Won-Jin Kim , Young-Wook Park , Jeong-Do Ryu
IPC分类号： H01L21/338 , H01L21/336
CPC分类号： H01L21/0209 , H01L21/302 , H01L21/6708 , H01L21/76895 , H01L27/10844 , H01L27/10882 , H01L29/7842
摘要： Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate. The at least one layer can be removed on the second side of the semiconductor substrate, while the capping layer and the pattern of the at least one layer is maintained on the first side of the semiconductor substrate. A portion of the capping layer can be removed on the first side of the semiconductor substrate.
摘要翻译：制造半导体器件的方法可以包括在半导体衬底的第一和第二侧上形成至少一个层。可以在半导体衬底的第一侧上去除至少一个层的部分，以在衬底的第一侧上形成至少一层的图案，同时将至少一层保持在衬底的第二面上。可以在衬底的第一侧上的至少一层的图案和半导体衬底的第二侧上的至少一个层上形成覆盖层。可以在半导体衬底的第二侧上去除覆盖层，从而在衬底的第二侧上保持覆盖层的同时暴露衬底的第二面上的至少一个层。可以在半导体衬底的第二侧上移除至少一个层，同时覆盖层和至少一层的图案保持在半导体衬底的第一侧上。可以在半导体衬底的第一侧上去除覆盖层的一部分。

2. 发明申请

US20080190030A1 Prefabricated Windows and Doors System 审中-公开
标题翻译：预制Windows和门系统
公开(公告)号：US20080190030A1
公开(公告)日：2008-08-14
申请号：US12066209
申请日：2006-09-08
申请人： Tae-Ho Cheon , Won-Jin Kim
发明人： Tae-Ho Cheon , Won-Jin Kim
IPC分类号： E05D15/06
CPC分类号： E06B3/4609 , E05D15/0665 , E05D15/0691 , E05Y2900/132 , E05Y2900/148
摘要： A prefabricated windows and doors system includes a window frame including upper and lower frame, a window holder suspended from the upper frame, a window support slidably inserted into the lower guide recess to support a roller, which is rotatable, on the rail, and a window coupled to the window holder and the window support, and being attachable to or removable from the window holder and the window support. The upper frame has an upper guide recess, and the lower frame contains a stepped portion to have a staircase shape and contains a lower guide recess on a sidewall of the stepped portion. A guide bar extended in a sliding direction of the window may be further installed in the upper guide recess. A suspension portion of the window holder may have a ring shape surrounding the guide bar.
摘要翻译：一种预制的门窗系统包括一个包括上框架和下框架的窗框，从上框架悬挂的窗户支架，可滑动地插入到下引导凹槽中的窗口支撑件，以支撑可转动的滚子在轨道上，窗口，其联接到窗户支架和窗户支撑件，并且可附接到窗户支架和窗户支撑件上或从窗户支架和窗户支架上移除。上框架具有上引导凹槽，并且下框架包含阶梯部分以具有阶梯形状并且在阶梯部分的侧壁上包含下引导凹部。沿着窗户的滑动方向延伸的导杆可以进一步安装在上引导凹槽中。窗口支架的悬挂部分可以具有围绕引导杆的环形形状。

3. 发明申请

US20070093063A1 Method of chemical mechanical polishing and method of fabricating semiconductor device using the same 失效
标题翻译：化学机械抛光方法及使用其制造半导体器件的方法
公开(公告)号：US20070093063A1
公开(公告)日：2007-04-26
申请号：US11585713
申请日：2006-10-24
申请人： Hyun-Suk Kim , Won-Jin Kim , Joon-Hee Lee , Yong-Seok Kim , Jong-Won Kim
发明人： Hyun-Suk Kim , Won-Jin Kim , Joon-Hee Lee , Yong-Seok Kim , Jong-Won Kim
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3212 , H01L27/105 , H01L27/11526 , H01L27/11531
摘要： There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer on the layer to be polished in the region where dishing may occur. Then, the layer to be polished is polished while dishing thereof is prevented using the dishing-preventing layer. Accordingly, the dishing-preventing layer is formed in the region where the dishing (i.e., over-polishing) may occur, so that the dishing is prevented from occurring in a region where pattern density is low and a pattern size is large in the process of CMP.
摘要翻译：提供了化学机械抛光（CMP）的方法和使用其的半导体器件的制造方法。该方法包括在包括正常抛光区域和碟形区域的半导体衬底上形成待抛光层，并且在可能发生凹陷的区域中在待抛光层上形成凹陷（即，过抛光） - 预防层。然后，使用防止凹陷层防止要抛光的层，同时使其抛光。因此，在可能发生凹陷（即，过度抛光）的区域中形成凹陷防止层，从而防止在图案密度低的区域和图案尺寸在该过程中发生凹陷的CMP。

4. 发明授权

US09946116B2 Liquid crystal display device having reduced color shift 有权
公开(公告)号：US09946116B2
公开(公告)日：2018-04-17
申请号：US13428942
申请日：2012-03-23
申请人： Joo Hong Seo , Jeong Uk Heo , Won Jin Kim , Seung Jin Kim , Sun-Jung Lee , Sang-Hun Jung , Min Hee Son
发明人： Joo Hong Seo , Jeong Uk Heo , Won Jin Kim , Seung Jin Kim , Sun-Jung Lee , Sang-Hun Jung , Min Hee Son
IPC分类号： G02F1/1343 , G02F1/1337 , G02F1/1362
CPC分类号： G02F1/133784 , G02F1/133707 , G02F1/134363 , G02F1/136227 , G02F1/136286 , G02F2001/134345 , G02F2001/134372
摘要： The present invention relates to a liquid crystal display device that prevents a color shift by allowing two sub-pixel areas to have the same transmittance. A liquid crystal display device according to the present invention includes a data line that includes: a connection portion having a direction of extension perpendicular to that of a gate line; a first portion oriented at a first angle with respect to a direction of extension of the connection portion; and a second portion oriented at a second angle different from the first angle with respect to the direction of extension of the connection portion, and wherein an angle between a rubbing direction of the liquid crystal and the connection portion satisfies θ L = θ 2 - θ 1 2 (where θL is the angle between the rubbing direction of the liquid crystal and the direction of extension of the connection portion, θ1: the first angle, θ2: the second angle).

5. 发明授权

US07745325B2 Wiring structure of a semiconductor device, method of forming the wiring structure, non-volatile memory device including the wiring structure, and method of manufacturing the non-volatile memory device 有权
标题翻译：半导体器件的布线结构，布线结构的形成方法，包括布线结构的非易失性存储器件以及非易失性存储器件的制造方法
公开(公告)号：US07745325B2
公开(公告)日：2010-06-29
申请号：US11798715
申请日：2007-05-16
申请人： Young-Ho Koh , Byung-Hong Chung , Won-Jin Kim , Hyun Park , Ji-Young Min
发明人： Young-Ho Koh , Byung-Hong Chung , Won-Jin Kim , Hyun Park , Ji-Young Min
IPC分类号： H01L21/00
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/76895 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.
摘要翻译：半导体器件的布线结构可以包括在衬底上的绝缘中间层，所述绝缘中间层具有具有第一宽度的线性第一沟槽和具有第二宽度的线性第二沟槽，所述线性第二沟槽与线性第一沟槽，第一宽度宽于第二宽度，以及在线性第一和第二沟槽中的导电层图案。

6. 发明授权

US07589022B2 Method of chemical mechanical polishing and method of fabricating semiconductor device using the same 失效
标题翻译：化学机械抛光方法及使用其制造半导体器件的方法
公开(公告)号：US07589022B2
公开(公告)日：2009-09-15
申请号：US11585713
申请日：2006-10-24
申请人： Hyun-Suk Kim , Won-Jin Kim , Joon-Hee Lee , Yong-Seok Kim , Jong-Won Kim
发明人： Hyun-Suk Kim , Won-Jin Kim , Joon-Hee Lee , Yong-Seok Kim , Jong-Won Kim
IPC分类号： H01L21/461
CPC分类号： H01L21/3212 , H01L27/105 , H01L27/11526 , H01L27/11531
摘要： There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer on the layer to be polished in the region where dishing may occur. Then, the layer to be polished is polished while dishing thereof is prevented using the dishing-preventing layer. Accordingly, the dishing-preventing layer is formed in the region where the dishing (i.e., over-polishing) may occur, so that the dishing is prevented from occurring in a region where pattern density is low and a pattern size is large in the process of CMP.
摘要翻译：提供了化学机械抛光（CMP）的方法和使用其的半导体器件的制造方法。该方法包括在包括正常抛光区域和碟形区域的半导体衬底上形成待抛光层，并且在可能发生凹陷的区域中在待抛光层上形成凹陷（即，过抛光） - 预防层。然后，使用防止凹陷层防止要抛光的层，同时使其抛光。因此，在可能发生凹陷（即，过度抛光）的区域中形成凹陷防止层，从而防止在图案密度低的区域和图案尺寸在该过程中发生凹陷的CMP。

7. 发明申请

US20080017889A1 Wiring structure of a semiconductor device, method of forming the wiring structure, non-volatile memory device including the wiring structure, and method of manufacturing the non-volatile memory device 有权
标题翻译：半导体器件的布线结构，布线结构的形成方法，包括布线结构的非易失性存储器件以及非易失性存储器件的制造方法
公开(公告)号：US20080017889A1
公开(公告)日：2008-01-24
申请号：US11798715
申请日：2007-05-16
申请人： Young-Ho Koh , Byung-Hong Chung , Won-Jin Kim , Hyun Park , Ji-Young Min
发明人： Young-Ho Koh , Byung-Hong Chung , Won-Jin Kim , Hyun Park , Ji-Young Min
IPC分类号： H01L23/52 , H01L21/44 , H01L29/739 , H01L21/82 , H01L27/10
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/76895 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.
摘要翻译：半导体器件的布线结构可以包括在衬底上的绝缘中间层，所述绝缘中间层具有具有第一宽度的线性第一沟槽和具有第二宽度的线性第二沟槽，所述线性第二沟槽与线性第一沟槽，第一宽度宽于第二宽度，以及在线性第一和第二沟槽中的导电层图案。

8. 发明授权

US07129174B2 Methods of fabricating a semiconductor substrate for reducing wafer warpage 失效
公开(公告)号：US07129174B2
公开(公告)日：2006-10-31
申请号：US10806521
申请日：2004-03-23
申请人： Won-Jin Kim , Young-Wook Park , Jeong-Do Ryu
发明人： Won-Jin Kim , Young-Wook Park , Jeong-Do Ryu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0209 , H01L21/302 , H01L21/6708 , H01L21/76895 , H01L27/10844 , H01L27/10882 , H01L29/7842
摘要： Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate. The at least one layer can be removed on the second side of the semiconductor substrate, while the capping layer and the pattern of the at least one layer is maintained on the first side of the semiconductor substrate. A portion of the capping layer can be removed on the first side of the semiconductor substrate.

9. 发明授权

US06649503B2 Methods of fabricating integrated circuit devices having spin on glass (SOG) insulating layers and integrated circuit devices fabricated thereby 失效
公开(公告)号：US06649503B2
公开(公告)日：2003-11-18
申请号：US09999624
申请日：2001-10-30
申请人： Won-Jin Kim , Jin-Gi Hong
发明人： Won-Jin Kim , Jin-Gi Hong
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/02063 , H01L21/02134 , H01L21/0217 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/3124 , H01L21/3125
摘要： Methods are provided for forming integrated circuit devices. A spin on glass (SOG) insulating layer is formed on an integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are formed on the sidewalls of the SOG insulating layer. Integrated circuit devices are also provided. The integrated circuit devices include an integrated circuit substrate, a spin on glass (SOG) insulating layer on the integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are provided on sidewalls of the SOG insulating layer.

10. 发明申请

US20080128021A1 NANOCOMPOSITE DEVICES, METHODS OF MAKING THEM, AND USES THEREOF 审中-公开
标题翻译：纳米复合器件，其制造方法及其用途
公开(公告)号：US20080128021A1
公开(公告)日：2008-06-05
申请号：US11850929
申请日：2007-09-06
申请人： Kaushik Roy Choudhury , Won Jin Kim , Yudhisthira Sahoo , Kwang Sup Lee , Paras N. Prasad , Alexander Cartwright , Ram B. Thapa
发明人： Kaushik Roy Choudhury , Won Jin Kim , Yudhisthira Sahoo , Kwang Sup Lee , Paras N. Prasad , Alexander Cartwright , Ram B. Thapa
IPC分类号： H01L31/04 , B05D5/12
CPC分类号： H01L51/426 , B82Y30/00 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0042 , Y02E10/549 , Y02P70/521
摘要： The present invention relates to a nanocomposite device comprising a polymeric matrix, semiconducting nanoparticles, and a semiconducting molecule having a field-effect mobility of at least 0.1 cm2/Vs. In addition, the present invention relates to a method of making a nanocomposite device. The method includes providing a mixture comprising a polymer, semiconducting nanoparticles, and a semiconducting molecule having a field-effect mobility of at least 0.1 cm2/Vs or a soluble precursor thereof, depositing the mixture on a substrate, and treating the mixture under conditions effective to produce a nanocomposite device comprising the polymeric matrix, semiconducting nanoparticles, and the semiconducting molecule having a field-effect mobility of at least 0.1 cm2/Vs. Thin film devices including the nanocomposite device are also disclosed.
摘要翻译：本发明涉及包含聚合物基质，半导体纳米颗粒和具有至少0.1cm 2 / Vs的场效应迁移率的半导体分子的纳米复合材料装置。另外，本发明涉及制造纳米复合器件的方法。该方法包括提供包含聚合物，半导体纳米颗粒和具有至少0.1cm 2 / Vs的场效应迁移率的半导体分子或其可溶性前体的混合物，将该混合物沉积在基底上并且在有效产生包含聚合物基质，半导体纳米颗粒和具有至少0.1cm 2 / Vs的场效应迁移率的半导体分子的纳米复合器件的条件下处理该混合物。还公开了包括纳米复合器件的薄膜器件。

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