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1. 发明申请

US20060076597A1 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 审中-公开
公开(公告)号：US20060076597A1
公开(公告)日：2006-04-13
申请号：US11235866
申请日：2005-09-26
申请人： Vishnu Agarwal , Garo Derderian , Gurtej Sandhu , Weimin Li , Mark Visokay , Cem Basceri , Sam Yang
发明人： Vishnu Agarwal , Garo Derderian , Gurtej Sandhu , Weimin Li , Mark Visokay , Cem Basceri , Sam Yang
IPC分类号： H01L29/94
CPC分类号： H01L28/84 , H01L21/02183 , H01L21/02197 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

2. 发明授权

US06940112B2 Integrated capacitors fabricated with conductive metal oxides 失效
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06940112B2
公开(公告)日：2005-09-06
申请号：US10234351
申请日：2002-08-30
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： C23C16/40 , H01L21/02 , H01L21/76
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuO x S）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

3. 发明授权

US06869877B2 Integrated capacitors fabricated with conductive metal oxides 失效
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06869877B2
公开(公告)日：2005-03-22
申请号：US10234581
申请日：2002-08-30
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： C23C16/40 , H01L21/02 , H01L21/44
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuOx）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

4. 发明授权

US06492241B1 Integrated capacitors fabricated with conductive metal oxides 有权
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06492241B1
公开(公告)日：2002-12-10
申请号：US09546492
申请日：2000-04-10
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： H01L2972
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuOx）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

5. 发明申请

US20060154382A1 Capacitor with high dielectric constant materials and method of making 审中-公开
标题翻译：具有高介电常数材料和制作方法的电容器
公开(公告)号：US20060154382A1
公开(公告)日：2006-07-13
申请号：US11346676
申请日：2006-02-03
申请人： Cem Basceri , Gurtej Sandhu , Mark Visokay
发明人： Cem Basceri , Gurtej Sandhu , Mark Visokay
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L28/56 , H01L27/10811
摘要： Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta2O5 and BaxSr(1-x)TiO3, and methods of making such capacitors and DRAM cells are provided. One method includes providing a conductive oxide electrode, oxidizing at least the upper surface of the conductive oxide electrode, depositing a first layer of a high dielectric constant oxide dielectric material on the conductive oxide electrode, oxidizing the first layer of the high dielectric constant oxide dielectric material under oxidizing conditions, depositing a second layer of the high dielectric constant oxide dielectric material on the first layer of the dielectric, and depositing an upper layer electrode on the second layer of the high dielectric constant oxide dielectric material.
摘要翻译：使用高介电常数氧化物介电材料如Ta 2 O 5和Ba x Sr（1-x）的稳定电容器和DRAM单元）和提供制造这种电容器和DRAM单元的方法。一种方法包括提供导电氧化物电极，至少氧化导电氧化物电极的上表面，在导电氧化物电极上沉积高介电常数氧化物电介质材料的第一层，氧化高介电常数氧化物电介质的第一层在氧化条件下的材料，在所述电介质的第一层上沉积高介电常数氧化物介电材料的第二层，以及在所述高介电常数氧化物介电材料的第二层上沉积上层电极。

6. 发明申请

US20090127656A1 Dielectric relaxation memory 有权
标题翻译：介质松弛记忆
公开(公告)号：US20090127656A1
公开(公告)日：2009-05-21
申请号：US12289692
申请日：2008-10-31
申请人： Cem Basceri , Gurtej Sandhu
发明人： Cem Basceri , Gurtej Sandhu
IPC分类号： H01L29/00
CPC分类号： H01L27/1085
摘要： A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.
摘要翻译：一种具有设置在两个导电电极之间的电介质层的电容器结构，其中所述电介质层包含对应于特定能量状态的至少一个电荷陷阱位置。能量状态可以用于区分电容器结构的存储器状态，从而允许本发明用作存储器件。形成陷阱的方法涉及在电介质层中的预定区域处的材料的原子层沉积。

7. 发明授权

US07388248B2 Dielectric relaxation memory 有权
标题翻译：介质松弛记忆
公开(公告)号：US07388248B2
公开(公告)日：2008-06-17
申请号：US10930774
申请日：2004-09-01
申请人： Cem Basceri , Gurtej Sandhu
发明人： Cem Basceri , Gurtej Sandhu
IPC分类号： H01L29/78 , H02H3/22
CPC分类号： H01L27/1085
摘要： A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition,of a material at pre-determined areas in the dielectric layer.
摘要翻译：一种具有设置在两个导电电极之间的电介质层的电容器结构，其中所述电介质层包含对应于特定能量状态的至少一个电荷陷阱位置。能量状态可以用于区分电容器结构的存储器状态，从而允许本发明用作存储器件。形成陷阱的方法涉及在电介质层中预定区域处的材料的原子层沉积。

8. 发明申请

US20070069270A1 Top electrode in a strongly oxidizing environment 审中-公开
标题翻译：顶极电极处于强氧化环境
公开(公告)号：US20070069270A1
公开(公告)日：2007-03-29
申请号：US11398498
申请日：2006-04-04
申请人： Cem Basceri , Howard Rhodes , Gurtej Sandhu , F. Gealy , Thomas Graettinger
发明人： Cem Basceri , Howard Rhodes , Gurtej Sandhu , F. Gealy , Thomas Graettinger
IPC分类号： H01L29/94
CPC分类号： H01L28/65 , H01L21/31637 , H01L21/31691 , H01L23/5222 , H01L27/10852 , H01L28/56 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies. The CIC sandwich further comprises a second conducting layer deposited over the first insulating layer in a strongly oxidizing ambient so as to reduce the concentration of oxygen vacancies in the first insulating layer, so as to provide an oxygen-rich interface layer between the first insulating layer and the second conducting layer, and so as to trap a plurality of oxygen atoms within the second conducting layer. The oxygen-rich interface layer and second conducting layer act as oxygen vacancy sinks for absorbing migrating oxygen vacancies that originate from the first insulating layer to thereby reduce the concentration of oxygen vacancies in the first insulating layer and to thereby reduce the buildup of oxygen vacancies at the interface layer. Thus, the first insulating layer provides an increased dielectric constant and an increased resistance to current flowing therethrough so as to increase the capacitance of the CIC sandwich and so as to reduce leakage currents flowing through the CIC sandwich.
摘要翻译：一种改进的电荷存储装置及其提供方法，电荷存储装置包括导体 - 绝缘体导体（CIC）三明治。 CIC夹层包括沉积在半导体集成电路上的第一导电层。 CIC夹层还包括以齐平方式沉积在第一导电层上的第一绝缘层。第一绝缘层包括具有多个氧化物和部分填充氧化物的多个氧原子的结构，其中未填充的氧气定义氧空位的浓度。 CIC夹层还包括在强氧化环境中沉积在第一绝缘层上的第二导电层，以便降低第一绝缘层中氧空位的浓度，从而在第一绝缘层之间提供富氧界面层和第二导电层，以便在第二导电层内捕获多个氧原子。富氧界面层和第二导电层用作氧空位吸收器，用于吸收源于第一绝缘层的迁移氧空位，从而降低第一绝缘层中氧空位的浓度，从而减少氧空位的累积接口层。因此，第一绝缘层提供增加的介电常数和增加的电流流过其中，从而增加CIC夹层的电容，并且减少流过CIC夹层的漏电流。

9. 发明申请

US20060292814A1 Methods of forming integrated circuitry 有权
公开(公告)号：US20060292814A1
公开(公告)日：2006-12-28
申请号：US11515432
申请日：2006-08-31
申请人： Cem Basceri , Gurtej Sandhu
发明人： Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L28/91
摘要： In one implementation, an opening within a capacitor electrode forming layer is formed over a substrate. A spacing layer is deposited over the capacitor electrode forming layer to within the opening over at least upper portions of sidewalls of the opening. The spacing layer is formed to be laterally thicker at an elevationally outer portion within the opening as compared to an elevationally inner portion within the opening. A spacer is formed within the opening by anisotropically etching the spacing layer. The spacer is laterally thicker at an elevationally outer portion within the opening as compared to an elevationally inner portion within the opening. After forming a first capacitor electrode layer laterally over the spacer, at least a portion of the spacer is removed and a capacitor dielectric region and a second capacitor electrode layer are formed over the first capacitor electrode layer.

10. 发明申请

US20060252221A1 Methods of forming hafnium-containing materials 有权
公开(公告)号：US20060252221A1
公开(公告)日：2006-11-09
申请号：US11485593
申请日：2006-07-11
申请人： Cem Basceri , F. Gealy , Gurtej Sandhu
发明人： Cem Basceri , F. Gealy , Gurtej Sandhu
IPC分类号： H01L21/20 , H01L21/31 , H01L21/8242
CPC分类号： H01G4/33 , H01G4/1209 , H01G4/1272 , H01L21/31645 , H01L27/10852 , H01L28/60 , H01L28/65 , H01L28/90 , H01L28/91 , H01L29/7833
摘要： The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are utilized to form hafnium-containing seed material in a desired crystalline phase and orientation over the substrate. Subsequently, second reaction conditions are utilized to grow second hafnium-containing material over the seed material. The second hafnium-containing material is in a crystalline phase and/or orientation different from the crystalline phase and orientation of the hafnium-containing seed material. The second hafnium-containing material can be, for example, in an amorphous phase. The seed material is then utilized to induce a desired crystalline phase and orientation in the second hafnium-containing material. The invention also includes capacitor constructions utilizing hafnium-containing materials, and circuit assemblies comprising the capacitor constructions.

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