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1. 发明授权

US5135880A Method of manufacturing a semiconductor device 失效
公开(公告)号：US5135880A
公开(公告)日：1992-08-04
申请号：US203662
申请日：1988-06-07
申请人： Carole A. Fisher , David H. Paxman , Philip H. Bird
发明人： Carole A. Fisher , David H. Paxman , Philip H. Bird
IPC分类号： H01L21/8234 , H01L21/8236 , H01L27/04 , H01L27/07 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7816 , H01L21/8234 , H01L21/8236 , H01L27/0727 , H01L27/0883 , H01L29/7801 , H01L29/7802 , H01L29/0615 , H01L29/41766 , H01L29/42368
摘要： A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9). First and second insulated gates (12) are provided on first and second areas (31a) and (31b), respectively, of the given surface to provide a respective gate connection between each source region and the associated drain region (10). The relative doses of impurities introduced to provide the second regions (5) and the relatively lightly doped drain extensions (11) received by the first area (31a) and the second area (31b) are independently controlled so as to provide adjacent the first area (31a) a channel area (13) of a second conductivity type and adjacent the second area (31b) a channel area (13') of the first conductivity.

2. 发明授权

US5229633A High voltage lateral enhancement IGFET 失效
标题翻译：高电压横向增强IGFET
公开(公告)号：US5229633A
公开(公告)日：1993-07-20
申请号：US822492
申请日：1992-01-17
申请人： Carole A. Fisher , David H. Paxman , Philip H. Bird
发明人： Carole A. Fisher , David H. Paxman , Philip H. Bird
IPC分类号： H01L21/8234 , H01L21/8236 , H01L27/07 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/31111 , H01L21/31144 , H01L21/32137 , H01L21/8234 , H01L21/8236 , H01L27/0727 , H01L27/0883 , H01L29/063 , H01L29/1095 , H01L29/66681 , H01L29/7801 , H01L29/7821 , H01L29/7823 , H01L29/7838 , H01L29/402 , H01L29/41741 , H01L29/42368
摘要： A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9). First and second insulated gates (12) are provided on first and second areas (31a) and (31b), respectively, of the given surface to provide a respective gate connection between each source region and the associated drain region (10). The relative doses of impurities introduced to provide the second regions (5) and the relatively lightly doped drain extensions (11) received by the first area (31a) and the second area (31b) are independently controlled so as to provide adjacent the first area (31a) a channel area (13) of a second conductivity type and adjacent the second area (31b) a channel area (13') of the first conductivity type.
摘要翻译：描述了包括增强（1）绝缘栅场效应晶体管（IGFET）和耗尽（2）模式IGFET两者的半导体器件的制造方法。杂质被引入到与半导体本体（3）的给定表面（3a）相邻的一种导电类型的第一区域或外延层（4）中，以为增强模式（1）和耗尽模式（2）提供两者， IGFET是与给定表面相邻的相反导电类型的第二区域（5），与给定表面（3a）相邻并被第二区域（5）包围的第一导电类型的源极区域（9）和漏极区域 10），其具有与给定表面相邻并且朝向源极区域（9）延伸的相对轻掺杂的漏极延伸区域（11）。第一和第二绝缘栅极（12）分别设置在给定表面的第一和第二区域（31a）和（31b）上，以在每个源极区域和相关联的漏极区域（10）之间提供相应的栅极连接。导入以提供由第一区域（31a）和第二区域（31b）接收的第二区域（5）和相对轻掺杂的漏极延伸部分（11）的杂质的相对剂量被独立地控制，以便邻近第一区域（31a）具有第二导电类型的沟道区域（13）并且邻近所述第二区域（31b）具有所述第一导电类型的沟道区域（13'）。

3. 发明授权

US4929884A High voltage semiconductor with integrated low voltage circuitry 失效
标题翻译：具有集成低压电路的高压半导体
公开(公告)号：US4929884A
公开(公告)日：1990-05-29
申请号：US203407
申请日：1988-06-06
申请人： Philip H. Bird , David J. Coe , David H. Paxman , Aart G. Korteling
发明人： Philip H. Bird , David J. Coe , David H. Paxman , Aart G. Korteling
IPC分类号： G05F1/56 , G05F3/24 , H01L27/088 , H01L27/092 , H01L29/78 , H03K17/06 , H03K17/082 , H03K17/567
CPC分类号： H01L27/0922 , G05F3/24 , H03K17/06 , H03K17/0822
摘要： Low voltage semiconductor devices are integrated monolithically with a high voltage semiconductor device on an electrically conductive substrate. The substrate forms an electrode of the high voltage device and is connected in use to the high voltage terminal of a power supply. The low voltage devices operate from a regulated low voltage supply, which is regulated with reference to the high voltage supply voltage, and not with reference to ground. This reduces the need to isolate the low voltage devices from the conductive substrate. An intelligent power switch circuit constructed in accordance with the invention is suitable for use in automotive and lighting applications.

4. 发明授权

US4771223A Motor speed control system 失效
标题翻译：电机调速系统
公开(公告)号：US4771223A
公开(公告)日：1988-09-13
申请号：US40910
申请日：1987-04-21
申请人： Desmond R. Armstrong , Philip H. Bird
发明人： Desmond R. Armstrong , Philip H. Bird
IPC分类号： H02P25/04 , H02P23/00 , H02P25/14 , H02P27/02 , H02P5/40
CPC分类号： H02P25/145 , H02P23/0077 , Y10S388/912
摘要： A speed control system for an a.c. electric motor (1) comprises a microcomputer (6) having an interrupt signal input (INT/TO) to which is coupled the outputs of a detector (10) for detecting zero-crossings of the a.c. supply voltage and a tachogenerator (11) driven by the motor. The microcomputer supplies firing pulses to a triac (2), connected in series with the motor, in response to an overflow of a clocked counter (CT). This counter is suitably preloaded at each zero-crossing. The counter is read each time a tachogenerator pulse occurs and the time which this reading indicates has elapsed since the immediately preceding zero-crossing is stored. A record is also kept in a register (ZCSLTA) of how many zero-crossings occur between each tachogenerator pulse and the next and from this, and the stored times relating to the relevant pulses, the period of the tachogenerator pulses and hence the actual speed of the motor is calculated. The preloading value for the counter is calculated from this and the required speed.
摘要翻译：一种速度控制系统。电动机（1）包括具有中断信号输入（INT / TO）的微计算机（6），耦合到检测器（10）的输出端，用于检测交流的过零点。电源电压和由电机驱动的测速发电机（11）。微计算机响应时钟计数器（CT）的溢出，向与电动机串联连接的三端双向可控硅开关元件（2）提供点火脉冲。该计数器在每个过零点处适当预加载。每当发生测速发电机脉冲并且从紧接在前的过零点开始经过该读取指示的时间之后，读取计数器。记录也保存在一个登记册（ZCSLTA）中，每个测速发电机脉冲和下一个测速发生器脉冲之间发生多少过零点，以及与相关脉冲相关的存储时间，测速发电机脉冲的周期以及因此的实际速度的电机计算。计数器的预加载值由此和所需速度计算。

5. 发明授权

US5289278A Duo-binary and/or binary data slicer 失效
标题翻译：二进制和/或二进制数据切片器
公开(公告)号：US5289278A
公开(公告)日：1994-02-22
申请号：US838049
申请日：1992-02-19
申请人： Philip H. Bird
发明人： Philip H. Bird
IPC分类号： H03K5/08 , H04N7/083 , H04N7/08
CPC分类号： H03K5/084 , H03K5/082 , H04N7/083
摘要： A duo-binary and/or binary data slicer has a data input (10) coupled via a capacitor (C1) to a d.c. restoring circuit (A2 to Q6 and Q9 to Q13) d.c. reference level is superimposed on the data signal. A sample and hold circuit (C2, Q15 to Q22) is arranged to sample the data signal and provide a voltage related to the upper and lower peak value. A divider (R16-R19) is coupled between the d.c. reference level and the voltage related to the upper and lower peak value and provides intermediate output voltages (DU, DL, B) relating to duo-binary and/or binary level for determining the slicing levels.
摘要翻译：二进制和/或二进制数据限幅器具有经由电容器（C1）耦合到直流电的数据输入端（10）。恢复电路（A2至Q6和Q9至Q13）d.c. 参考电平叠加在数据信号上。采样和保持电路（C2，Q15至Q22）被布置为对数据信号进行采样并提供与上下峰值相关的电压。分频器（R16-R19）耦合在直流电源参考电平和与上下峰值相关的电压，并提供与二进制和/或二进制电平相关的中间输出电压（DU，DL，B）以确定限幅电平。

6. 发明授权

US4890020A Circuit for driving a semiconductor device with protection against transients 失效
标题翻译：用于驱动具有防止瞬变的半导体器件的电路
公开(公告)号：US4890020A
公开(公告)日：1989-12-26
申请号：US231911
申请日：1988-05-27
申请人： Philip H. Bird
发明人： Philip H. Bird
IPC分类号： H03K17/08 , G05F1/56 , H01L21/822 , H01L27/04 , H02H7/12 , H02M3/155 , H03K17/00 , H03K17/0412 , H03K17/082
CPC分类号： H03K17/0822 , H03K17/04123 , H03K2217/0036
摘要： An arrangement for driving a power semiconductor device (1) has an input (12) for receiving a control signal and a control output (11) for connection to the control electrode (9) of the power semiconductor device (1). The semiconductor device connected in series with a load (5) across a power supply (3,6). The arrangement includes an active turn-off device (T67) to achieve fast turn-off of the device (1). The arrangement further includes a threshold detecting means (29) which operates to turn on the semiconductor device in the event of a high voltage transient on the power supply. This reduces the voltage across the semiconductor device and hence reduces power dissipation within the semiconductor during transients. The turn-off device (T67) could be damaged by high transient currents when the threshold detecting means (29) conducts, so a further threshold detecting means (30) acts to disable the turn-off means (T67) during transients. The arrangement may be integrated monolithically with an associated semiconductor output device. An intelligent power switch circuit including such an arrangement is suitable for use in a motor vehicle.

7. 发明授权

US4885477A Differential amplifier and current sensing circuit including such an amplifier 失效
标题翻译：差分放大器和电流检测电路包括这样的放大器
公开(公告)号：US4885477A
公开(公告)日：1989-12-05
申请号：US203404
申请日：1988-06-06
申请人： Philip H. Bird , Desmond R. Armstrong
发明人： Philip H. Bird , Desmond R. Armstrong
IPC分类号： H03F3/345 , H03F3/34 , H03F3/347 , H03F3/45
CPC分类号： H03F3/45076
摘要： A differential amplifier includes first and second matched field-effect transistors (FETs) (21,22) having their source electrodes connected together and to a current source (2), and their drain electrodes connected respectively to an input and an output of a current mirror circuit (3). The FETs (21,22) are depletion-mode FETs, and the current source comprises parallel-connected third and fourth depletion-mode FETs (25,26) matched to the first and second FETs (21,22). The current source (2) and current mirror (3) act to constrain the first and second FETs (21,22), to operate over a predetermined operating curve, for which they are optimally matched to one another. The differential amplifier may be constructed as an integrated circuit, and may form part of a circuit for sensing current in a power semiconductor device.

8. 发明授权

US4941050A An afc arrangement for tuning a television receiving apparatus to a select transmission having an actual carrier frequency which differs from a nominal carrrier frequency 失效
标题翻译：一种用于将电视接收装置调谐到具有不同于名义载波频率的实际载波频率的选择传输的afc装置
公开(公告)号：US4941050A
公开(公告)日：1990-07-10
申请号：US338927
申请日：1989-04-14
申请人： Philip H. Bird
发明人： Philip H. Bird
IPC分类号： H03J7/04 , H04N5/50 , H04N7/20
CPC分类号： H03J7/047 , H04N5/50
摘要： A television receiver has an a.f.c. arrangement for ensuring the correct tuning of a tuner unit (4) which is tuned to the nominal carrier frequency by a tuning voltage (VT). When the tuner unit (4) is incorrectly tuned to the actual carrier frequency, the a.f.c. system operates in a first mode in which a sweep current produced by a current source (15) is applied by way of a closed switch (16) to an a.f.c. capacitor (17) to produce a swept a.f.c. voltage for the tuner unit (4). The sweep direction is controlled by an RS flip-flop (13) by way of a multiplexer (12) in response to voltage comparators (19, 20) connected to the a.f.c. capacitor (17). When the tuning is sufficiently close such that the received transmission can be correctly decoded, the a.f.c. arrangement goes into a second mode in which the output of a frequency demodulator (6) is applied via the multiplexer (12) to control the current source (15) and hence the voltage across a.f.c. capacitors (17). For this second mode gate pulses (G1, G2) from a processor (11) control the multiplexer (12) paths by a monostable (14) and only cause the switch (16) to be conductive during a given portion of each line period.

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