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1. 发明授权

US4904614A Method of manufacturing lateral IGFETS including reduced surface field regions 失效
标题翻译：制造横向IGFETS的方法，包括减少的表面场区域
公开(公告)号：US4904614A
公开(公告)日：1990-02-27
申请号：US197539
申请日：1988-05-23
申请人： Carole A. Fisher , David H. Paxman , David J. Coe
发明人： Carole A. Fisher , David H. Paxman , David J. Coe
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66681 , H01L29/1095 , H01L29/66674 , H01L29/7816 , H01L29/7835 , H01L29/0615 , H01L29/0847 , H01L29/7393
摘要： A method of manufacturing a semiconductor device such as a lateral insulated gate field effect transistor is described in which impurities for forming first and second relatively shallow RESURF regions (8 and 11) of the opposite and the one conductivity type, respectively, are then introduced into the first region (4) and the semiconductor body is then heated first in an oxidizing atmosphere to cause the impurities to diffuse to form the RESURF regions (8 and 11) and to grow a relatively thick layer of insulating material on the given surface (3) at the same time. The relatively thick layer of insulating material is then defined to provide field oxide (14a) and gate oxide (14) then grown onto which is deposited a conductive gate layer (15,16) to form an insulated gate structure. Impurities are then introduced into the semiconductor body (3) using the insulated gate structure as a mask so as to form a lateral insulated gate field effect transistor (1).

2. 发明授权

US5229633A High voltage lateral enhancement IGFET 失效
标题翻译：高电压横向增强IGFET
公开(公告)号：US5229633A
公开(公告)日：1993-07-20
申请号：US822492
申请日：1992-01-17
申请人： Carole A. Fisher , David H. Paxman , Philip H. Bird
发明人： Carole A. Fisher , David H. Paxman , Philip H. Bird
IPC分类号： H01L21/8234 , H01L21/8236 , H01L27/07 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/31111 , H01L21/31144 , H01L21/32137 , H01L21/8234 , H01L21/8236 , H01L27/0727 , H01L27/0883 , H01L29/063 , H01L29/1095 , H01L29/66681 , H01L29/7801 , H01L29/7821 , H01L29/7823 , H01L29/7838 , H01L29/402 , H01L29/41741 , H01L29/42368
摘要： A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9). First and second insulated gates (12) are provided on first and second areas (31a) and (31b), respectively, of the given surface to provide a respective gate connection between each source region and the associated drain region (10). The relative doses of impurities introduced to provide the second regions (5) and the relatively lightly doped drain extensions (11) received by the first area (31a) and the second area (31b) are independently controlled so as to provide adjacent the first area (31a) a channel area (13) of a second conductivity type and adjacent the second area (31b) a channel area (13') of the first conductivity type.
摘要翻译：描述了包括增强（1）绝缘栅场效应晶体管（IGFET）和耗尽（2）模式IGFET两者的半导体器件的制造方法。杂质被引入到与半导体本体（3）的给定表面（3a）相邻的一种导电类型的第一区域或外延层（4）中，以为增强模式（1）和耗尽模式（2）提供两者， IGFET是与给定表面相邻的相反导电类型的第二区域（5），与给定表面（3a）相邻并被第二区域（5）包围的第一导电类型的源极区域（9）和漏极区域 10），其具有与给定表面相邻并且朝向源极区域（9）延伸的相对轻掺杂的漏极延伸区域（11）。第一和第二绝缘栅极（12）分别设置在给定表面的第一和第二区域（31a）和（31b）上，以在每个源极区域和相关联的漏极区域（10）之间提供相应的栅极连接。导入以提供由第一区域（31a）和第二区域（31b）接收的第二区域（5）和相对轻掺杂的漏极延伸部分（11）的杂质的相对剂量被独立地控制，以便邻近第一区域（31a）具有第二导电类型的沟道区域（13）并且邻近所述第二区域（31b）具有所述第一导电类型的沟道区域（13'）。

3. 发明授权

US06632709B2 Electronic device manufacture 有权
标题翻译：电子设备制造
公开(公告)号：US06632709B2
公开(公告)日：2003-10-14
申请号：US09821130
申请日：2001-03-29
申请人： John R. A. Ayres , Stanley D. Brotherton , Carole A. Fisher , Frnak W. Rohlfing , Nigel D. Young
发明人： John R. A. Ayres , Stanley D. Brotherton , Carole A. Fisher , Frnak W. Rohlfing , Nigel D. Young
IPC分类号： H01L2100
CPC分类号： H01L29/66757 , H01L29/78609 , H01L29/78621 , H01L2029/7863
摘要： A method of fabricating an electronic device comprising a thin-film transistor, which addresses a problem of increased off-state current and reduced carrier mobility in self-aligned thin-film transistors. According to the method, a gate layer (2,46) is etched back underneath a mask layer (20,48). Following an implantation step using the mask layer as an implantation mask, the etch-back exposes implant damage which is then annealed by an energy beam (42).
摘要翻译：一种制造包括薄膜晶体管的电子器件的方法，其解决了自对准薄膜晶体管中增加的截止电流和降低的载流子迁移率的问题。根据该方法，在掩模层下面（ 20,48 ）蚀刻栅极层（ 2,46 ）。在使用掩模层作为注入掩模的注入步骤之后，蚀刻暴露植入物损伤，然后通过能量束（ 42 ）退火。

4. 发明授权

US5135880A Method of manufacturing a semiconductor device 失效
公开(公告)号：US5135880A
公开(公告)日：1992-08-04
申请号：US203662
申请日：1988-06-07
申请人： Carole A. Fisher , David H. Paxman , Philip H. Bird
发明人： Carole A. Fisher , David H. Paxman , Philip H. Bird
IPC分类号： H01L21/8234 , H01L21/8236 , H01L27/04 , H01L27/07 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7816 , H01L21/8234 , H01L21/8236 , H01L27/0727 , H01L27/0883 , H01L29/7801 , H01L29/7802 , H01L29/0615 , H01L29/41766 , H01L29/42368
摘要： A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9). First and second insulated gates (12) are provided on first and second areas (31a) and (31b), respectively, of the given surface to provide a respective gate connection between each source region and the associated drain region (10). The relative doses of impurities introduced to provide the second regions (5) and the relatively lightly doped drain extensions (11) received by the first area (31a) and the second area (31b) are independently controlled so as to provide adjacent the first area (31a) a channel area (13) of a second conductivity type and adjacent the second area (31b) a channel area (13') of the first conductivity.

5. 发明授权

US4892838A Method of manufacturing an insulated gate field effect transistor 失效
标题翻译：绝缘栅场效应晶体管的制造方法
公开(公告)号：US4892838A
公开(公告)日：1990-01-09
申请号：US197542
申请日：1988-05-23
申请人： Carole A. Fisher , David H. Paxman
发明人： Carole A. Fisher , David H. Paxman
IPC分类号： H01L21/336 , H01L29/06 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/66674 , H01L29/7801 , H01L29/0615 , H01L29/42368 , Y10S148/163
摘要： A method of manufacturing a semiconductor device in which a lateral insulated gate field effect transistor (IGFET) (1) is provided by defining an insulated gate structure (12) on a given surface (3a) of a semiconductor body (3) by providing an insulating layer on the given surface (3a) having a relatively thin region on a first area of the given surface adjoining a relatively thin region (14a) on a second area (31b) of the given surface and providing a conductive layer (15,16) on the insulating layer to define an insulated gate over the first area of the given surface with the conductive layer extending up onto the relatively thick region of the insulating layer. A window (26) is opened in the conductive layer on the relatively thick region of the insulating layer and the insulating layer is then etched isotropically through the window in the conductive layer to form a window (25) in the relatively thick region of the insulating layer thereby leaving part (29) of the conductive layer overhanging the edge of the window in the insulating layer. The conductive layer is then selectively etched with at least the area of the conductive layer spaced from the window masked so as to remove the part (29) overhanging the edge of the window (25) in the insulating layer. Impurities are then introduced using the insulated gate structure (12) as a part of a mask to form a source region (9) aligned with the insulated gate and a drain region (10) aligned with the window in the conductive layer (15, 16).

6. 发明授权

US4754315A Bipolar semiconductor devices with implanted recombination region 失效
标题翻译：具有植入复合区的双极半导体器件
公开(公告)号：US4754315A
公开(公告)日：1988-06-28
申请号：US825846
申请日：1986-02-04
申请人： Carole A. Fisher , David H. Paxman , Reginald C. Oldfield
发明人： Carole A. Fisher , David H. Paxman , Reginald C. Oldfield
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/167 , H01L29/732 , H01L29/72 , H01L29/06 , H01L29/74
CPC分类号： H01L29/167 , H01L29/1004
摘要： A bipolar semiconductor device with interdigitated emitter and base regions has a sub-region of the base, which has a shorter carrier recombination time than the major part of the base region due to the presence of argon ion implantation induced carrier recombination centers. The sub-region of the base is located centrally with respect to the emitter region to intercept the transient current lines during device turn-off and so to promote collapse of the transient current and the avoidance of second breakdown of the device. The centrally located sub-region of the base is remote from the emitter region edges to collector region current flow when the device is on. The ions may be implanted at energies between 50 keV and 3 MeV and at doses between 10.sup.11 ions cm.sup.-2 and 10.sup.14 ions cm.sup.-2. The implanatation mask may be provided by photolithographically processed resist having a thickness between 0.5 .mu.m and 4 .mu.m dependant on the ion implantation energy. The depth of the sub region and the concentration of recombination centers within the sub-region may be varied by altering the implantation conditions to tailor the effect of the sub-region to the likelihood of the onset of second breakdown at any part of a device structure. The invention is particularly of use in transistors, and in thyristors.
摘要翻译：具有交叉发射极和基极区域的双极半导体器件具有基极的子区域，由于存在氩离子注入诱导的载流子复合中心，其具有比基极区域的主要部分更短的载流子复合时间。基极的子区域相对于发射极区域位于中心，以在器件关断期间截取瞬态电流线，并且因此促进瞬态电流的崩溃并避免器件的第二次击穿。当设备打开时，基座的中心位置的子区域远离发射极区域边缘到集电极区域电流。离子可以在50keV和3MeV之间的能量下以1011离子cm -2和1014离子cm -2之间的剂量注入。植入掩模可以根据离子注入能量由光刻处理的抗蚀剂提供，其厚度在0.5μm和4μm之间。子区域的深度和子区域内的复合中心的浓度可以通过改变注入条件来改变，以将子区域的影响定义为器件结构的任何部分处的第二次击穿开始的可能性。本发明特别用于晶体管和晶闸管中。

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