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1. 发明申请

US20050089126A1 Transparent multi-mode PAM interface 有权
标题翻译：透明多模PAM接口
公开(公告)号：US20050089126A1
公开(公告)日：2005-04-28
申请号：US10805413
申请日：2004-03-19
申请人： Jared Zerbe , Carl Werner , William Stonecypher , Fred Chen
发明人： Jared Zerbe , Carl Werner , William Stonecypher , Fred Chen
IPC分类号： H04L1/00 , H04L5/14 , H04L25/02 , H04L25/03 , H04L25/49 , H04L27/08 , H03K9/02 , H03K7/02
CPC分类号： H04L27/08 , H04L1/0003 , H04L5/1438 , H04L25/028 , H04L25/0292 , H04L25/4917 , H04L2025/03585
摘要： Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols in constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.
摘要翻译：提供了一种用于高速，多模式PAM符号传输的方法和装置。多模式PAM输出驱动器根据PAM模式信号的状态驱动一个或多个符号，用于一个或多个符号的PAM调制中使用的级别数。另外，一个或多个符号以符号率被驱动，符号速率是根据PAM模式信号选择的符号速率，使得驱动符号的数据速率相对于PAM模式信号的状态的变化是恒定的。还提供了用于在给定物理环境中确定用于符号传输和接收的PAM最优数量的方法。

2. 发明授权

US07180957B2 Technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system 失效
标题翻译：利用在多级信令系统中使用转移限制码产生的备用带宽的技术
公开(公告)号：US07180957B2
公开(公告)日：2007-02-20
申请号：US10667355
申请日：2003-09-23
申请人： Anthony Bessios , William Stonecypher , Jared Zerbe , Carl Werner
发明人： Anthony Bessios , William Stonecypher , Jared Zerbe , Carl Werner
IPC分类号： H04L25/34 , H04L25/49
CPC分类号： H04L25/4915 , H04L25/4919
摘要： A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic wherein a signal level is periodically unused. Such a method may comprise modifying the transition-limiting code such that the periodically unused signal level is used to represent additional information.
摘要翻译：公开了一种利用在多级信令系统中使用转移限制码产生的备用带宽的技术。在一个特定示例性实施例中，该技术可以被实现为用于在多级信令系统中利用由转换限制码使用产生的备用带宽的方法，其中转移限制码具有其中信号电平为定期未使用这种方法可以包括修改转换限制码，使得周期性地使用的信号电平用于表示附加信息。

3. 发明申请

US20060242483A1 Built-in self-testing of multilevel signal interfaces 审中-公开
标题翻译：内置多电平信号接口的自检
公开(公告)号：US20060242483A1
公开(公告)日：2006-10-26
申请号：US11433409
申请日：2006-05-12
申请人： Carl Werner , Jared Zerbe , William Stonecypher
发明人： Carl Werner , Jared Zerbe , William Stonecypher
IPC分类号： G01R31/28
CPC分类号： G11C11/56 , G01R31/31715 , G11C11/22 , G11C16/04 , G11C29/00 , G11C29/50 , G11C2029/5004
摘要： Error detection mechanisms for signal interfaces, including built-in self-test (BIST) mechanisms for testing multilevel signal interfaces. The error detection mechanisms are provided in an integrated circuit (IC) chip that contains at least one of the signal interfaces or are coupled to the interfaces on a printed circuit board (PCB). BIST mechanisms may include, for example, test signal generators and mechanisms for determining whether the test signals generated are accurately transmitted and received by the interface. The BIST mechanisms may check a single input/output interface, a group of interfaces or may operate with a master device that tests a plurality of interfaces by sending test signals for storage by and retrieval from one or more slave memory devices. The error detection mechanisms test memory circuits designed to communicate according to multi-PAM signals over printed circuit boards.
摘要翻译：用于信号接口的错误检测机制，包括用于测试多电平信号接口的内置自检（BIST）机制。误差检测机构提供在集成电路（IC）芯片中，该集成电路（IC）芯片包含至少一个信号接口或耦合到印刷电路板（PCB）上的接口。 BIST机制可以包括例如测试信号发生器和用于确定生成的测试信号是否被接口准确地发送和接收的机制。 BIST机制可以检查单个输入/输出接口，一组接口，或者可以通过发送用于由一个或多个从属存储器设备存储和检索的测试信号来测试多个接口的主设备进行操作。错误检测机构根据印刷电路板上的多PAM信号测试设计用于通信的存储器电路。

4. 发明授权

US07180958B2 Technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system 失效
标题翻译：利用在多级信令系统中使用转移限制码产生的备用带宽的技术
公开(公告)号：US07180958B2
公开(公告)日：2007-02-20
申请号：US10849153
申请日：2004-05-20
申请人： Anthony Bessios , William Stonecypher , Carl Werner , Jared Zerbe
发明人： Anthony Bessios , William Stonecypher , Carl Werner , Jared Zerbe
IPC分类号： H04L25/34 , H04L25/49
CPC分类号： H04L25/4915 , H04L25/4919
摘要： A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic such that at least one signal level is periodically unused. The method comprises utilizing the at least one periodically unused signal level in a codeword that has been encoded using the transition-limiting code so as to represent additional information in the multi-level signaling system.
摘要翻译：公开了一种利用在多级信令系统中使用转移限制码产生的备用带宽的技术。在一个特定示例性实施例中，该技术可以被实现为用于利用在多级信令系统中使用转换限制代码而产生的备用带宽的方法，其中转移限制码具有这样的特征，使得至少一个信号电平周期性未使用。该方法包括利用已经使用转移限制码编码的码字中的至少一个周期性不使用的信号电平，以便表示多电平信令系统中的附加信息。

5. 发明申请

US20070064510A1 Method And Apparatus For Evaluating And Optimizing A Signaling System 有权
标题翻译：用于评估和优化信号系统的方法和装置
公开(公告)号：US20070064510A1
公开(公告)日：2007-03-22
申请号：US11559111
申请日：2006-11-13
申请人： Jared Zerbe , Pak Chau , William Stonecypher
发明人： Jared Zerbe , Pak Chau , William Stonecypher
IPC分类号： G11C29/00
CPC分类号： H04L1/244 , G01R31/31703 , G01R31/31713 , G01R31/31716 , G01R31/31717 , G01R31/3183 , G01R31/31855 , G01R31/318577 , G01R31/3187 , G06F11/221 , G06F11/26 , G06F13/423 , G11C29/02 , G11C29/022 , G11C29/025 , G11C29/40 , H04B1/04 , H04B1/16 , H04B3/32 , H04B17/0085 , H04L1/0001 , H04L1/242 , H04L1/243 , H04L5/1438 , H04L25/03885
摘要： A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
摘要翻译：描述了用于评估和优化信令系统的方法和装置。在系统的发送电路中产生测试信息的模式，并将其发送到接收电路。在接收电路中产生类似的信息模式并用作参考。接收电路比较图案。模式之间的任何差异是可观察的。在一个实施例中，实现线性反馈移位寄存器（LFSR）以产生模式。本公开的实施例可以用各种类型的信令系统来实施，包括具有单端信号和具有差分信号的信令系统。本公开的实施例可以应用于在给定时间在单个导体上传送单个信息位的系统以及同时在单个导体上传送多个信息位的系统。

6. 发明申请

US20060022724A1 Method and apparatus for fail-safe resynchronization with minimum latency 有权
公开(公告)号：US20060022724A1
公开(公告)日：2006-02-02
申请号：US11237276
申请日：2005-09-27
申请人： Jared Zerbe , Michael Ching , Abhijit Abhyankar , Richard Barth , Andy Chan , Paul Davis , William Stonecypher
发明人： Jared Zerbe , Michael Ching , Abhijit Abhyankar , Richard Barth , Andy Chan , Paul Davis , William Stonecypher
IPC分类号： H03L7/00
CPC分类号： G06F1/12 , G06F13/423 , H03L7/085 , H04L7/0012 , H04L7/0045 , H04L7/0054 , H04L7/02 , H04L7/0337
摘要： A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

7. 发明授权

US07765074B2 Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit 有权
标题翻译：用于从时钟数据恢复（CDR）单元捕获波形的表示的电路，装置和方法
公开(公告)号：US07765074B2
公开(公告)日：2010-07-27
申请号：US11445702
申请日：2006-06-02
申请人： Dennis Kim , Jared Zerbe , Mark Horowitz , William Stonecypher
发明人： Dennis Kim , Jared Zerbe , Mark Horowitz , William Stonecypher
IPC分类号： G06F19/00
CPC分类号： H03L7/0814 , H03L7/091 , H04L7/0083 , H04L7/033 , H04L7/044 , H04L7/10
摘要： A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.
摘要翻译：电路，装置和方法使用相移数据采样时钟在接收电路获得系统余量，同时允许CDR在实施例中与输入数据流保持同步。在一个实施例中，电路包括第一和第二采样器，用于对数据信号进行采样，并响应于数据时钟信号和边沿时钟信号输出数据和边缘信息。相位检测器响应于数据信息和边缘信息产生相位信息。时钟相位调整电路在同步模式期间响应于数据信息产生数据时钟信号和边沿时钟信号。时钟相位调整电路在波形捕获模式期间递增数据时钟信号的相位。

8. 发明申请

US20060236183A1 METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM 有权
标题翻译：用于评估和优化信号系统的方法和装置
公开(公告)号：US20060236183A1
公开(公告)日：2006-10-19
申请号：US11422474
申请日：2006-06-06
申请人： Jared Zerbe , Pak Chau , William Stonecypher
发明人： Jared Zerbe , Pak Chau , William Stonecypher
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G01R31/31717 , G01R31/31703 , G01R31/3183 , G06F11/221 , H04B3/32
摘要： A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
摘要翻译：描述了用于评估和优化信令系统的方法和装置。在系统的发送电路中产生测试信息的模式，并将其发送到接收电路。在接收电路中产生类似的信息模式并用作参考。接收电路比较图案。模式之间的任何差异是可观察的。在一个实施例中，实现线性反馈移位寄存器（LFSR）以产生模式。本公开的实施例可以用各种类型的信令系统来实施，包括具有单端信号和具有差分信号的信令系统。本公开的实施例可以应用于在给定时间在单个导体上传送单个信息位的系统以及同时在单个导体上传送多个信息位的系统。

9. 发明申请

US20070165472A1 METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM 审中-公开
标题翻译：用于评估和优化信号系统的方法和装置
公开(公告)号：US20070165472A1
公开(公告)日：2007-07-19
申请号：US11686706
申请日：2007-03-15
申请人： Jared Zerbe , Pak Chau , William Stonecypher
发明人： Jared Zerbe , Pak Chau , William Stonecypher
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： H04L1/244 , G01R31/31703 , G01R31/31713 , G01R31/31716 , G01R31/31717 , G01R31/3183 , G01R31/31855 , G01R31/318577 , G01R31/3187 , G06F11/221 , G06F11/26 , G06F13/423 , G11C29/02 , G11C29/022 , G11C29/025 , G11C29/40 , H04B1/04 , H04B1/16 , H04B3/32 , H04B17/0085 , H04L1/0001 , H04L1/242 , H04L1/243 , H04L5/1438 , H04L25/03885
摘要： A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
摘要翻译：描述了用于评估和优化信令系统的方法和装置。在系统的发送电路中产生测试信息的模式，并将其发送到接收电路。在接收电路中产生类似的信息模式并用作参考。接收电路比较图案。模式之间的任何差异是可观察的。在一个实施例中，实现线性反馈移位寄存器（LFSR）以产生模式。本公开的实施例可以用各种类型的信令系统来实施，包括具有单端信号和具有差分信号的信令系统。本公开的实施例可以应用于在给定时间在单个导体上传送单个信息位的系统以及同时在单个导体上传送多个信息位的系统。

10. 发明申请

US20060224339A1 Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit 有权
公开(公告)号：US20060224339A1
公开(公告)日：2006-10-05
申请号：US11445702
申请日：2006-06-02
申请人： Dennis Kim , Jared Zerbe , Mark Horowitz , William Stonecypher
发明人： Dennis Kim , Jared Zerbe , Mark Horowitz , William Stonecypher
IPC分类号： G01R13/00
CPC分类号： H03L7/0814 , H03L7/091 , H04L7/0083 , H04L7/033 , H04L7/044 , H04L7/10
摘要： A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

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